FPGA Designer Lead
Sainte-Anne-de-Bellevue, QCMDA
15+ YOECandidates need a bachelor's degree in electrical engineering or equivalent and 15+ years designing or architecting FPGAs or ASICs, including technical leadership of an FPGA team. Strong French and ideally English communication, teamwork, and a reliability security clearance are required.
Synplify, ModelSim, Xilinx Vivado, Microchip Libero, Jira, Confluence
FPGA Designer
Sainte-Anne-de-Bellevue, QCMDA
5+ YOECandidates need a bachelor's degree in electrical engineering or equivalent and five years of FPGA or ASIC design experience. They need VHDL skills, tool knowledge (Synplify, Questa, Vivado, Libero), Linux scripting, and bilingual English and French communication.
Synplify, Modelsim, Questa, Vivado, Libero, Jira