Design Verification Engineer — Memory Subsystem (Vancouver)
Vancouver, BCOn-site
QC
Qualcomm Canada ULC
3+ YOECandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.
Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers