Design Verification Engineer (PCIe)
CanadaFull Time
H
HCLTech
Candidates need hands-on SystemVerilog and UVM design verification experience and PCIe Gen3/Gen4/Gen5 protocol verification skills, with knowledge of PCIe architecture, LTSSM and the transaction, data link and physical layers. Strong debugging and analytical skills are also required.
SystemVerilog, UVM, VCS, Xcelium, Questa