“ASIC simulation and synthesis tools” jobs in Canada – Page 2

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• 1mo

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in computer or electrical engineering, and strong Verilog or SystemVerilog RTL design skills. Experience delivering ASIC or FPGA products, plus networking or high-speed interface knowledge, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  1mo

  Principal ASIC Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a track record of leading ASIC or silicon designs through multiple tape-outs, plus deep RTL and microarchitecture skills. A bachelor's degree in an engineering or computer field is preferred, and a master's or PhD is desired.

  Verilog, SystemVerilog, Python, Perl, Tcl

• 1mo

  Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)

  Markham, ON

  On-site

  

  Qualcomm Canada ULC

  2+ YOECandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.

  SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools

• 1mo

  SMTS Logic Design

  Montréal, QC

  

  Rambus: As an industry pioneer with over 30 years experience, Rambus is a premier provider of chips & silicon IP.

  8+ YOECandidates need a BS, MS or PhD in electrical or computer engineering, 8+ years of ASIC/SoC logic design experience, and expert SystemVerilog skills. Experience with synthesis, timing closure and PCIe Gen5/Gen6/Gen7 is preferred.

  SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, SpyGlass, Questa

• 1mo

  Senior/Expert Hardware Design Engineer - FPGA

  Montréal, QC

  On-siteFull Time

  

  Sopra Steria: The Group provides end-to-end solutions to make large companies and organisations more competitive by combining in-depth knowledge of a wide range…

  5+ YOECandidates need a bachelor's or master's degree in electrical or electronic engineering and at least 5 years of FPGA design experience with Xilinx devices or airborne electronic hardware. They also need Vivado, VHDL or Verilog, video pipeline experience, and fluency in French and English.

  Vivado, VHDL, Verilog, SystemVerilog, DisplayPort, HDMI

• 1mo

  High Level Synthesis Compiler Engineer

  Toronto, ON

  Full Time

  AS

  Altera Semiconductor Technology Canada ULC

  8+ YOECandidates need a Bachelor's or Master's degree in an engineering or computer science field and 8+ years building compilers, LLVM/MLIR tools or EDA/FPGA software. They must know production C++, MLIR or LLVM, FPGA design and implementation flows, and be able to mentor engineers and work with customers.

  C++, LLVM, MLIR

• 1mo

  FPGA Compiler (Placer) Engineer

  Toronto, ON

  Full Time

  A

  Altera

  6+ YOECandidates need 6+ years in FPGA or ASIC CAD, EDA tools or physical design, strong algorithms skills, and C/C++ experience. A bachelor's or master's in electrical, computer engineering or computer science is required.

  Quartus, Vivado, C++, Python, Tcl

• 1mo

  Senior FPGA Design/Verification Engineer

  Ottawa, ON

  Full Time

  LO

  Lumentum Ottawa ULC

  Candidates need strong experience designing and simulating FPGA or ASIC logic in Verilog or SystemVerilog, plus synthesis, timing and clock domain crossing skills. Strong debugging, communication and attention to detail are also required.

  Verilog, SystemVerilog, Altera FPGA tools

  1mo

  FPGA Designer

  Ottawa, ON

  Full Time

  LO

  Lumentum Ottawa ULC

  Candidates need experience designing ASIC or FPGA logic in Verilog or SystemVerilog, including synthesis, timing and clock domain crossing, plus AMD (Xilinx) or Altera tools. Strong debugging skills and clear communication are required.

  Xilinx, Altera, Verilog, SystemVerilog

• 1mo

  Senior SoC Design Engineer

  Burnaby, BC

  $86k–$186k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  3+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.

  Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl

• 1mo

  ASIC Front End Implementation Engineer

  Ottawa, ON

  Full Time

  CC

  Ciena Canada ULC

  5+ YOECandidates need a B.Sc. in electrical or computer engineering and 5+ years of ASIC digital design and DFT experience. They must have hands-on DFT and synthesis tool skills and be able to work well in engineering teams.

  Synthesis tools, Static timing analysis tools, DFT tools, EDA tools

• 1mo

  Hardware Intern - AI HW & SoC (Canada)

  Ottawa, ON +1

  

  Tenstorrent University Jobs: Tenstorrent is a next-generation computing company that builds computers for AI.

  Candidates need to be students in EE, ECE, CE or CS with coursework in digital design and computer architecture. They should know ASIC concepts such as RTL, verification, logic synthesis and timing analysis, and have scripting or programming skills.

  Python, C++, PERL, tcl, architectural simulator

• 1mo

  Sr. Principal Program Manager, ASIC Design

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  10+ YOEAstera Labs needs a candidate with 10+ years in ASIC or SoC development, including 3+ years in technical program management. Candidates need hands-on knowledge of the chip design flow, EDA and CAD tools, and pre-silicon validation.

  CAD infrastructure, Emulation platforms, FPGA prototyping platforms

• 1mo

  Senior ASIC (Front End) Design Engineer

  Toronto, ON

  Hybrid

  

  Ethernovia, Inc.

  10+ YOECandidates need a BS or MS in electrical engineering, computer science or a related field and 10+ years of ASIC RTL design or architecture experience. They must have built complex SoCs, know Verilog/SystemVerilog and simulation tools, and work well both independently and in teams.

  Verilog, Perl, TCL, C/C++, Make

12 companies