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Positron AI
8+ YOEPositron AI needs 8+ years of ASIC development with several production tapeouts, deep DFT experience, and hands-on Siemens Tessent. Candidates also need Verilog/SystemVerilog RTL skills, synthesis and gate-level verification, and scripting in Python, Tcl or Perl.
Siemens Tessent, Verilog, SystemVerilog, Python, Tcl, Perl
Collabera
3+ YOECandidates need commercial firmware experience in neural network processing or machine learning, plus compiler and optimization experience. Strong C/C++ skills and embedded multiprocessor experience are required, along with debugging skills using JTAG.
JTAG, FPGA, Caffe, schematics
onsemi: With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety,…
3+ YOECandidates need a Bachelor's or Master's degree in an engineering discipline and 3-5 years of embedded firmware experience. Strong embedded C, microprocessor and communication protocol knowledge (UART, I2C, SPI, USB) and experience with AI-assisted development tools are required.
Git, JIRA, FPGA, oscilloscope, logic analyzer, hardware debugger
BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.
10+ YOECandidates need 10 or more years of hands-on ASIC verification experience through tape-out sign-off, strong SystemVerilog and UVM skills, and experience with high-speed interfaces or die-to-die interconnect. Scripting, regression automation and clear written communication are essential.
SystemVerilog, UVM, UPF
Rambus: As an industry pioneer with over 30 years experience, Rambus is a premier provider of chips & silicon IP.
8+ YOECandidates need a BS, MS or PhD in electrical or computer engineering, 8+ years of ASIC/SoC logic design experience, and expert SystemVerilog skills. Experience with synthesis, timing closure and PCIe Gen5/Gen6/Gen7 is preferred.
SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, SpyGlass, Questa
SiFive, Inc.
Candidates need experience with concurrency-sensitive upstream Linux kernel code, debugging hardware and software bugs in CPUs and SoCs, and working with CPU architects. They also need experience with Linux on FPGA or emulation, hypervisors, and familiarity with the RISC-V architecture.
Linux kernel, OpenSBI, hardware debuggers, FPGA, emulation platforms
Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.
Candidates need deep knowledge of computer architecture and chip microarchitecture, plus hands-on RTL design in Verilog or VHDL and familiarity with full ASIC flows. Experience optimizing for power, performance and area, and working collaboratively on specifications and design reviews, is needed. Prior work on on-chip fabric or interconnect design is an asset.
Verilog, VHDL, FPGA, UVM, emulation platforms
Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
10+ YOEAstera Labs needs a candidate with 10+ years in ASIC or SoC development, including 3+ years in technical program management. Candidates need hands-on knowledge of the chip design flow, EDA and CAD tools, and pre-silicon validation.
CAD infrastructure, Emulation platforms, FPGA prototyping platforms
Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
2+ YOECandidates need a bachelor's degree in electrical or electronics engineering, 2 to 5 years of digital design experience on complex chips, and hands-on SystemVerilog or Verilog RTL skills. PCIe or Ethernet IP experience and Python or Perl scripting are also required, and candidates must be authorized to work in Canada.
SystemVerilog, Verilog, Synopsys, Cadence, Python, Perl
Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
2+ YOECandidates need a bachelor's degree in electrical engineering or a related field and 2 to 5 years of verifying complex chips. Hands-on SystemVerilog, UVM and C/C++ experience, including C/C++ integration with SystemVerilog, is required, as is authorization to work in Canada.
SystemVerilog, UVM, C/C++, Python, Perl, FPGA emulation platform
Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
8+ YOECandidates need a bachelor's degree in a technical field and 8 to 12 years of embedded firmware experience. They must know embedded C/C++, Ethernet or high-speed connectivity hardware, and analog or mixed-signal tuning. A master's degree and Python or lab-instrument experience are preferred.
Oscilloscope, BERT, Logic analyzer, GDB, Git, Jenkins
10 companies