Analog and RF Layout Engineer
Toronto, ONCapgemini
6+ YOECandidates need 6+ years of analog, RF or mixed-signal IC layout experience, including advanced FinFET nodes at 7nm and below. They need hands-on skill with Cadence, Synopsys or Siemens EDA tools and strong knowledge of DRC, LVS and reliability constraints.
Synopsys, Siemens EDA, Mentor Graphics