Analog Design, Principal Engineer- 18339
Markham, ONSynopsys
8+ YOECandidates need 8+ years of CMOS analog or mixed-signal design experience and strong expertise in transistor-level and SerDes circuits. Hands-on FinFET layout, SPICE and scripting skills, and knowledge of reliability and ESD design are also required.
SPICE simulators, EDA tools, Python, TCL
Analog Design, Manager - 18463
Kanata, ONSynopsys
8+ YOE2+ MgmtCandidates need an M.A.Sc. with 8+ years or a PhD with 6+ years of analog or mixed-signal IC design experience, plus 2+ years of people management. They must have deep Multi-Gbps SerDes expertise, transistor-level design skills, and experience with SPICE, Verilog-A and layout.
SPICE, Verilog-A, Industry-standard simulation tools
Principal SI/PI Engineer - 18619
Mississauga, ONSynopsys
12+ YOECandidates need a bachelor's degree (master's or PhD preferred) in electrical engineering and 12+ years of high-speed SI/PI experience on SerDes links. They also need strong skills in simulation tools, lab measurement and scripting, plus proven technical leadership.
HSPICE, Keysight ADS, SystemVue, Ansys HFSS, SIwave, AEDT
Hardware Validation Engineer, Sr Staff
Nepean, ONSynopsys
6+ YOECandidates need 6-8+ years of high-speed hardware design and validation experience and expert Cadence Allegro skills. They also need strong signal integrity knowledge, bench debugging experience and familiarity with JTAG, I2C, SPI and UART interfaces.
Cadence Allegro, logic analyzer, oscilloscope, VNA, spectrum analyzer, protocol analyzer