RTL Design Engineer – PCIe
CanadaContract
Y
Yochana
Candidates need hands-on RTL design experience in Verilog or SystemVerilog and PCIe Gen3/Gen4/Gen5 verification experience. They should understand FSM design, CDC, reset architecture, synchronizers, low-power design, synthesis constraints and timing, and have strong debugging skills.
Verilog, SystemVerilog