Technology Lead-Memory Layout
CanadaInfosys
5+ YOECandidates need 5+ years of compiler or custom memory layout experience, including leafcell library design and FinFET layout at 5nm and 3nm. They must know physical verification (DRC, LVS, ERC) and use Cadence Virtuoso and Calibre, plus a bachelor's degree or equivalent experience.
Cadence Virtuoso, Calibre
Technology Lead - Data Engineer
CanadaInfosys
4+ YOECandidates need at least 4 years of IT experience with hands-on data engineering or ETL/ELT work, plus a bachelor's degree or equivalent experience. Strong Python, SQL and Linux shell scripting skills are required, with cloud data platform experience.
Python, Snowflake, Azure Data Factory, Microsoft Fabric, SQL, UNIX/Linux shell