Design Verification Engineer — Memory Subsystem (Vancouver)
Vancouver, BCQualcomm Canada ULC
3+ YOECandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.
Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers
Clocking Systems Engineer, Staff
Toronto, ONQualcomm Canada ULC
4+ YOEQualcomm Canada ULC needs a bachelor's degree with 4+ years, a master's with 3+ years, or a PhD with 2+ years of systems engineering experience. Candidates need clocking, mixed-signal, SerDes or PLL/CDR experience, and skills in MATLAB, Python or SystemVerilog.
MATLAB, Python, SystemVerilog
Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)
Markham, ONQualcomm Canada ULC
2+ YOECandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.
SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools
FY27 Intern - Compute DSP/AI Processor Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
1+ YOECandidates need to be enrolled toward a bachelor's degree in engineering or computer science, available May or June 2027 to August or September 2028, and have digital design knowledge with Verilog or VHDL. Strong problem-solving, communication and teamwork skills are also required.
SystemVerilog, Verilog, VHDL, UVM, SystemC, Python