Principal DSP Firmware Engineer
Ottawa, ONMCHP Semiconductor Canada ULC
6+ YOECandidates need an MSc or PhD in electrical or computer engineering or a related field, plus at least 6 years of DSP or embedded software experience. Strong C/C++, Python, TCL and RTOS skills are required, along with good debugging and communication skills.
C/C++, Python, TCL, Jira, Git, Confluence
Principal Engineer - Design
Burnaby, BCMCHP Semiconductor Canada ULC
10+ YOEMicrochip Semiconductor Canada ULC needs candidates with a BS or MS in electrical or computer engineering and 10+ years of experience. Strong skills in serial protocols, Linux, C, Python and HDL design are required.
Cadence Palladium, Cadence Protium, FPGA, protocol analyzers, test and defect tracking tools
Principal Engineer -Design
Saskatoon, SKMCHP Semiconductor Canada ULC
10+ YOECandidates need 10 years of experience in synthesis, static timing analysis and formal verification, plus tapeout experience on 16nm or smaller processes. Strong scripting skills and a degree in computer science or electrical/VLSI engineering are required.
Cadence Genus, TCL, Perl, Python, UPF, CPF
Sr Engineer I - Validation (Systems)
Burnaby, BCMCHP Semiconductor Canada ULC
5+ YOECandidates need at least 5 years of silicon or SoC validation experience, strong C/C++ and Python (or Tcl) skills, and hands-on lab work with high-speed test equipment. A bachelor's or master's degree in computer or electrical engineering or computer science is required.
Oscilloscopes, Protocol analyzers, Logic analyzers, FPGAs, Validation boards, Lab equipment
Principal Engineer - Validation (Systems)
Burnaby, BCMCHP Semiconductor Canada ULC
10+ YOECandidates need 10 years of silicon or SoC validation experience, strong C/C++ and Python skills, and hands-on lab experience with high-speed test equipment. A Bachelor's or Master's in electrical or computer engineering or computer science is required.
Oscilloscope, Protocol analyzer, Logic analyzer, FPGA, Emulation platform, Validation board
Technical Staff Engineer - Design
Burnaby, BCMCHP Semiconductor Canada ULC
12+ YOECandidates need a B.S. in electrical engineering with 12+ years of related experience, hands-on pad ring and bump map work for advanced SoC designs, and knowledge of IO standards such as SerDes, DDR, PCIe and CXL. Scripting skills in Tcl or Python are required.
Orbit IO, ISP, Tcl, Python, Verilog, SVN
Software Engineer
Toronto, ONMCHP Semiconductor Canada ULC
7+ YOECandidates need a degree in computer science or electrical or computer engineering, 7+ years of software experience, strong C/C++ skills and at least 2 years working with LLVM/MLIR. A solid grasp of digital design and algorithms is also required.
LLVM, MLIR, Git, Python, TCL, Bash
Senior Engineer - Analog Design
Ottawa, ONMCHP Semiconductor Canada ULC
3+ YOECandidates need a Master's or PhD in Electrical Engineering and about 3 to 5 years of analog or mixed-signal IC design experience. They should know PLLs, ADCs, filters or high-speed I/O and use Cadence IC design tools.
Cadence IC design tools, Verilog-A, Skill, Python, Perl, Tcl
Senior Technical Staff Engineer - Analog Design
Ottawa, ONMCHP Semiconductor Canada ULC
10+ YOECandidates need a Master's or Doctorate in Electrical Engineering or a related field and 10+ years of analog and mixed-signal IC design experience, including PLLs, DLLs, ADCs, DACs and high-speed I/O. Strong skills in Cadence tools, scripting and multi-site teamwork are required.
Cadence, Verilog-A, Skill, Python, Perl, Tcl
Ingénieur principal du personnel technique – Conception analogique/ Senior Technical Staff Engineer - Analog Design
Montréal, QCMCHP Semiconductor Canada ULC
10+ YOEMaîtrise ou doctorat en génie électrique; Plus de 10 ans d’expérience en circuits intégrés analogiques et mixtes; Expérience en PLL/DLL, ADC/DAC et interfaces E/S haute vitesse
Cadence IC, Verilog-A, Skill, Python, Perl, Tcl
Manager- Validation Design Engineering
Burnaby, BCMCHP Semiconductor Canada ULC
12+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering, 12+ years of related experience including leading engineering teams, and coaching and developing engineers. Hands-on knowledge of high-speed interfaces such as PCI Express and Ethernet, FPGA and test automation, and lab instruments is preferred.
oscilloscopes, BERT, VNA, protocol analyzers, FPGA platforms, 1.6T Ethernet testers
Senior Manager-Design Engineering
Burnaby, BC +2MCHP Semiconductor Canada ULC
12+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering, 12+ years of related experience and proven experience leading engineering teams. Strong coaching skills, debugging ability and Verilog or VHDL design experience are required; SOC, communication protocols, Synopsys or Cadence tools and 28nm process experience are assets.
Verilog, VHDL, Synopsys, Cadence