Sr. Engineer, Staff Analog Design
Ottawa, ONSiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…
10+ YOECandidates need a Master's or PhD in Electrical Engineering, 10+ years in analog/mixed-signal CMOS design, and PLL design experience. Cadence tools and lab characterization experience are also required.
Cadence, SystemVerilog, Verilog-A
Human Resources Business Partner
CanadaSiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…
5+ YOECandidates need a bachelor's degree in HR, business or a related field, 5+ years of HR experience including HRBP work, and strong coaching, consulting and influencing skills. Experience with engineering or manufacturing teams is preferred.
Performance management, Employee relations, Coaching, Leadership, Onboarding
Engineer, Staff Analog Design
Ottawa, ONSiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…
6+ YOECandidates need a Master's or PhD in Electrical Engineering and 6+ years of analog or mixed-signal IC design, including PLL design, CMOS or BiCMOS experience, and hands-on lab characterization.
Cadence, SystemVerilog, Verilog-A, AMS
ASIC Digital Verification Engineer
Ottawa, ONSiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…
Candidates need knowledge of chip specifications and verification plans, plus SystemVerilog and UVM for digital verification. Experience with Synopsys or Cadence simulators, SystemVerilog assertions, functional and code coverage, and working in Unix/Linux is also needed.
SystemVerilog, UVM, Unix, Linux