Analog Design, Sr Architect - 18729
Markham, ONSynopsys
12+ YOECandidates need at least 12 years of related experience in high-speed interfaces and mixed-signal design. They also need skills in custom analog design, simulation, verification, debugging, and writing technical specifications.
Documentation, Communication skills, Troubleshooting, Debugging
Principal Digital Verification Engineer
Nepean, ONSynopsys
12+ YOESynopsys candidates need 12+ years of verification experience with a BSc, 10+ years with an MSc, or 8+ years with a PhD. They need deep SystemVerilog and UVM skills, simulation and waveform debugging, C knowledge, assertion-based verification, and Linux scripting. Experience with LPDDR5/5X or LPDDR6 and emulation platforms is a plus.
SystemVerilog, UVM, waveform debugger, Linux, source control, emulation platform
Principal SerDes Architect
Mississauga, ONSynopsys
10+ YOECandidates need 10+ years in high-speed analog, SerDes or optical communications, with knowledge of IEEE 802.3, OIF and PCIe optical specifications. A BS or MS in Electrical Engineering, Physics or a related field is required, and a PhD is preferred.
ICT system integration, Troubleshooting, Regulatory compliance, Optical components, Photonics, Documentation
Silicon Validation Engineer
Mississauga, ONSynopsys
6+ YOECandidates need a Master's in electrical or electronics engineering with 6+ years of post-silicon validation experience, or a Bachelor's with 7+ years. Hands-on lab skill with BERTs, oscilloscopes, VNAs and TDRs, plus MATLAB and Python, is required.
BERT, real-time oscilloscope, sampling oscilloscope, VNA, TDR, MATLAB
Senior Staff Hardware Validation Engineer
Mississauga, ONSynopsys
6+ YOESynopsys needs a bachelor's degree in electrical or electronic engineering with 8 years of relevant experience, or a master's with 6 years. Candidates need lab test equipment experience, PCB fabrication house experience and skill running PI and SI simulations.
HFSS, high-speed scopes, power meters, IR cameras, FPGA development tools, Verilog HDL
ASIC Digital Verification, Sr. Manager
Mississauga, ONSynopsys
15+ YOECandidates need a BS or MS in EE, EC or VLSI with 15+ years of IP or SoC verification experience, and strong team leadership. They must know Verilog, SystemVerilog and UVM, and Perl or Python automation. PCIe and Ethernet knowledge is an asset.
Verilog, SystemVerilog, UVM, Perl, Python