“Synopsys tools” jobs in Canada – Page 5

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• 1mo

  Logistics Coordinator

  Oakville, ON

  $60k–$75k/yrFull Time

  

  Randstad Canada

  1+ YOECandidates need 1 to 3 years of experience in transportation coordination, 3PL logistics or inventory management, plus hands-on TMS and WMS experience and post-secondary education in supply chain, logistics or business. Strong communication, problem-solving and attention to detail are essential.

  Teds Transportation, WMS, TMS, Excel, MS Teams

  1mo

  Contracts Specialist

  Milton, ON

  $30–$37/hrContract

  

  Randstad Canada

  Candidates need proven commercial contract drafting experience, ideally in manufacturing, plus knowledge of contract and corporate law and strong negotiation skills. Proficiency in Microsoft Office and CRM or contract tools is also required.

  MS CRM, Microsoft Word, Microsoft Excel, Microsoft PowerPoint, Microsoft Outlook, Legal databases

  1mo

  DevOps Engineer

  Montréal, QC

  Contract

  

  Randstad Canada

  3+ YOECandidates need 3 to 5 years of DevOps or infrastructure automation experience, with Azure, Terraform, Packer, GitHub Actions and PowerShell skills. Knowledge of PostgreSQL and MySQL backup workflows and a bachelor's degree or equivalent experience are also needed.

  Terraform, Packer, Azure, Azure VMware Solution, GitHub Actions, GitHub Copilot

• 1mo

  Sr. Manager Packaging Engineering

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's degree or higher in electrical, computer or mechanical engineering, plus proven leadership of complex concurrent projects. Experience in semiconductor package design, high-speed layout, OSAT and substrate work, and tools such as Synopsys 3DICC or Cadence SiP/APD is preferred.

  Synopsys 3DICC, Cadence SiP, Cadence APD

  1mo

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in computer or electrical engineering, and strong Verilog or SystemVerilog RTL design skills. Experience delivering ASIC or FPGA products, plus networking or high-speed interface knowledge, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  1mo

  3D IC and ADVANCED PACKAGING CAD ENGINEER

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering, experience with 3D-IC design and advanced packaging, and hands-on work with Synopsys 3DIC Compiler. Strong scripting skills and experience applying AI to CAD or hardware design are also needed.

  Synopsys 3DIC Compiler, Synopsys EDA tools, Cadence EDA tools, Linux/Unix, Python, TCL

  1mo

  Physical Design Engineer

  Vancouver, BC

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering and hands-on ASIC physical design experience from RTL to GDSII. Strong Verilog, timing analysis, low-voltage design and advanced-node tape-out experience (3nm to 16nm) are preferred.

  Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog

  1mo

  Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need strong SystemVerilog and UVM skills, solid ASIC/SoC verification experience, and familiarity with constrained-random, coverage-driven and formal (SVA) methods. A bachelor's or master's in computer or electrical engineering is required.

  Synopsys VCS, Cadence IES, Cadence IEV, Jasper, VC-Formal, Magellan

  1mo

  Physical Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  8+ YOECandidates need a bachelor's, master's or PhD in electrical, electronics or computer engineering, with 8, 4 or 2 years of physical design experience respectively. They need expertise in block-level place and route, timing closure, physical verification and power, performance and area optimization, plus hands-on debugging of EDA tools from Synopsys, Cadence and Siemens.

  Synopsys ICC2, Cadence Innovus, Synopsys PrimeTime, Spyglass, RedHawk, Calibre

  1mo

  Physical Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates at Advanced Micro Devices need ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and hands-on tape-out experience on 3nm to 16nm SoCs. They also need experience with Synopsys, Cadence or Mentor Graphics CAD tools and a bachelor's or master's degree in electrical or computer engineering.

  Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog

  1mo

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs candidates with proven SoC implementation and tapeout experience, deep knowledge of equivalence checking and low power verification, and hands-on use of industry EDA tools. Strong scripting, debugging, leadership and communication skills are also required, along with a BS or MS in Electrical Engineering, ECE, EEE or a related field.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

  1mo

  Lead Physical Design Engineer, Place & Route

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need deep hands-on place-and-route experience on complex chip designs, including timing closure and physical verification. Experience with Synopsys Fusion Compiler, Cadence and Siemens EDA tools, plus TCL, Perl or Shell scripting, is preferred, and a Bachelor's or Master's degree in electrical or computer engineering is preferred.

  Synopsys Fusion Compiler, Cadence, Siemens EDA, TCL, Perl, Shell

  1mo

  SoC Physical Design Implementation Lead

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs seasoned physical design experience on advanced nodes, with hands-on place and route, timing and sign-off skills. Candidates should know Synopsys, Cadence and Siemens tools and scripting in Tcl, Perl or Shell; a Bachelor's or Master's in electrical or computer engineering is preferred.

  Synopsys tools, Cadence tools

• 1mo

  Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)

  Markham, ON

  On-site

  

  Qualcomm Canada ULC

  2+ YOECandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.

  SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools

• 1mo

  ASIC Verification Engineer (7745)

  Ottawa, ON

  T

  TSMC

  5+ YOECandidates need a master's or PhD in electrical or computer engineering and 5-10 years of digital verification experience. They should be strong in SystemVerilog, UVM, assertions, Unix/Linux and EDA tools such as VCS or Incisive.

  Synopsys VCS, Cadence Incisive, UVM, Unix/Linux

• 1mo

  HW & SW Applications Admin 1

  Toronto, ON

  

  Celestica International LP

  5+ YOECandidates need a bachelor's degree in computer science, software or electrical engineering, or a related field, and 5+ years of enterprise IT or application engineering experience, including 2+ years supporting an R&D engineering team. Hands-on experience with EDA/CAD suites, DevOps tools, license management and Linux and Windows environments is required.

  Azure DevOps, Jira, Git, Docker, Kubernetes, PTC Creo

• 1mo

  Analog and RF Layout Engineer

  Toronto, ON

  

  Capgemini

  6+ YOECandidates need 6+ years of analog and RF IC layout experience for high-speed applications, including advanced FinFET nodes (7nm and below). Hands-on use of Cadence, Mentor and Synopsys EDA tools and knowledge of floorplanning, routing and electromigration are required.

  Cadence, Mentor, Synopsys

  1mo

  Analog and RF Layout Engineer

  Toronto, ON

  

  Capgemini

  6+ YOECandidates need 6+ years of analog, RF or mixed-signal IC layout experience, including advanced FinFET nodes at 7nm and below. They need hands-on skill with Cadence, Synopsys or Siemens EDA tools and strong knowledge of DRC, LVS and reliability constraints.

  Synopsys, Siemens EDA, Mentor Graphics

• 1mo

  Senior Physical Design Engineer - P&R

  Ottawa, ON

  RemoteFull Time

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  8+ YOECandidates need 8 or more years of ASIC digital place-and-route experience, recent hands-on work with Synopsys and Cadence tools, and knowledge of advanced FinFET nodes. Scripting skills and strong written communication for remote teamwork are also required.

  Synopsys, Cadence, PrimeTime, StarRC, RedHawk, Calibre

• 1mo

  SMTS Logic Design

  Montréal, QC

  

  Rambus: As an industry pioneer with over 30 years experience, Rambus is a premier provider of chips & silicon IP.

  8+ YOECandidates need a BS, MS or PhD in electrical or computer engineering, 8+ years of ASIC/SoC logic design experience, and expert SystemVerilog skills. Experience with synthesis, timing closure and PCIe Gen5/Gen6/Gen7 is preferred.

  SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, SpyGlass, Questa

• 1mo

  Warehouse Production Supervisor

  Dartmouth, NS

  On-siteFull Time

  

  Graphite Innovation & Technologies: GIT Coatings (Graphite Innovation & Technologies Inc, www.gitcoatings.com) is a Canadian company developing sustainable graphene-based hull and…

  4+ YOEGraphite Innovation & Technologies asks for a minimum of 4 years combined experience in warehouse management and supervising production, a forklift licence, and English fluency. Candidates also need Microsoft Office skills and experience with WMS or ERP systems; a supply chain, engineering, logistics or business diploma is desirable.

  Forklift, Pallet jack, ERP system, Warehouse management system, Scanners, Microsoft Office

• 1mo

  Staff Software Engineer

  Toronto, ON

  Full Time

  EC

  Equifax Canada Co.

  7+ YOECandidates need a bachelor's degree or equivalent experience and 7+ years of hands-on software engineering with Java, Spring Boot, JavaScript/TypeScript, and cloud platforms (GCP, AWS or Azure). Experience designing microservices, CI/CD and infrastructure-as-code is required, and proficiency with AI coding tools is expected.

  Java, Spring Boot, GCP, Kubernetes, Terraform, Helm

• 1mo

  Principal Engineer -Design

  Saskatoon, SK

  Full Time

  MS

  MCHP Semiconductor Canada ULC

  10+ YOECandidates need 10 years of experience in synthesis, static timing analysis and formal verification, plus tapeout experience on 16nm or smaller processes. Strong scripting skills and a degree in computer science or electrical/VLSI engineering are required.

  Cadence Genus, TCL, Perl, Python, UPF, CPF

  1mo

  Senior SoC Design Engineer

  Burnaby, BC

  $86k–$186k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  3+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.

  Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl

11 companies