Application Engineer, Sr Staff
Toronto, ONQualcomm Canada ULC
6+ YOECandidates need a bachelor's degree in electrical or computer engineering plus 6 or more years of hardware experience, or an equivalent advanced degree with fewer years. They need strong debugging skills, C/C++ for embedded systems, and Python for test automation.
Oscilloscope, BERT, Protocol analyzer
Verification Engineer (Engineer–Senior Level)
Toronto, ONQualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in science or engineering with 2+ years of ASIC design or verification experience, or a master's with 1+ year, or a PhD. Strong SystemVerilog and UVM skills, constrained random verification experience and clear communication are required.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
Program Manager
Toronto, ONQualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in electrical engineering or a related field, plus experience in stage gate processes and high speed SerDes IP development. Scheduling skills in MS Project and familiarity with advanced process nodes at 5nm and below are also needed. A PMP certification is an asset.
MS Project
Firmware Engineer, Edge AI Silicon Validation (Embedded C)
Markham, ONQualcomm Canada ULC
2+ YOECandidates need at least 2 years of embedded firmware or silicon validation experience in C, plus a bachelor's degree and 4 or more years of ASIC validation work (or a master's with 3 years, or a PhD with 2 years). Strong debugging, lab equipment and communication skills are needed.
Oscilloscope, Protocol analyzer, JTAG debugger, FPGA prototyping system, Perforce, Git
Staff Verification Engineer, Compute Subsystems
Markham, ONQualcomm Canada ULC
5+ YOECandidates need a bachelor's, master's, or PhD in engineering or science with several years of ASIC design or verification experience, plus strong UVM and SystemVerilog skills, bus protocol knowledge, and scripting in Perl or Python.
UVM, Perl, Python, C
SOC Design Engineer
Markham, ON +2Qualcomm Canada ULC
4+ YOECandidates need a degree in science or engineering and 4+ years of ASIC design, verification or integration work, with strong digital front-end design skills in Verilog, SystemVerilog and VHDL. Experience with power domains, clock domain crossing, low-power design and chip design tools is needed.
Spyglass, Design Compiler, Cadence LEC, Perl, TCL
Camera Design Engineer
Vancouver, BCQualcomm Canada ULC
3+ YOECandidates need a bachelor's, master's or PhD in a computer, electrical or related engineering field, with 4 to 2 years of hardware or related experience depending on degree. Verilog or VHDL RTL design, design verification and bus protocol experience are key.
Verilog, VHDL, TCL, Perl, Python
ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a Bachelor's degree in engineering, science or a related field and 2+ years of ASIC design or verification work, or a new-grad co-op, internship or PEY background. Preferred skills include SystemVerilog, UVM, Verilog or VHDL, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python
ASICS Design Verification Engineer (Vancouver, Markham OR Remote)
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in engineering or science and 2+ years of ASIC design or verification experience. Preferred skills include SystemVerilog and UVM testbench development, RTL design, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python