Senior ASIC Design Engineer - DSP/Analog/SerDes
Ottawa, ONCelero Communications, Inc.
10+ YOECandidates need a master's or PhD in electrical or computer engineering, 10+ years of digital ASIC design, and strong Verilog or SystemVerilog skills. Knowledge of DSP, high-speed SerDes, mixed-signal or optical communications is also required.
Verilog, SystemVerilog, Python, Tcl, MATLAB, UVM
Optical DSP Design Engineer
Ottawa, ONCelero Communications, Inc.
2+ YOECandidates need a strong background in digital signal processing, digital communications and fiber-optic systems, plus a Master's or PhD in electrical engineering, physics or mathematics. Two or more years of industry experience and programming in C/C++, Python or MATLAB are preferred.
MATLAB, Python, C++, Verilog, VHDL, GitHub
DSP - FEC Design Engineer
Ottawa, ONCelero Communications, Inc.
Candidates need a strong background in coding theory, digital communications and error correction, plus experience with forward error correction for communication systems. A master's or PhD in a related field and programming skills in C/C++, Python or MATLAB are preferred.
MATLAB, Python, C++, GitHub, Verilog, VHDL