Verification Engineer
Markham, ONAMD, Inc.
Candidates need strong SystemVerilog and UVM skills, experience with ASIC or SoC verification, and familiarity with constrained-random, coverage-driven and formal verification. A Bachelor's or Master's in computer or electrical engineering is required.
UVM, Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal
SoC Lead Engineer – LEC & Low Power Signoff
Markham, ONAMD, Inc.
Candidates need proven SoC implementation and tapeout experience, in-depth LEC and low power static verification skills, and hands-on use of Formality or Conformal, VC-LP or CLP, and Design Compiler or Fusion Compiler. Verilog, VHDL, UPF, Tcl, Perl and Python skills and a BS/MS in electrical engineering or a related field are also expected.
Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler