“Verilog-A” jobs in Canada

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• 3d

  Principal Analog Mixed Signal Designer - 19497

  Mississauga, ON

  S

  Synopsys

  5+ YOECandidates need a PhD with 5+ years or a Master's with 8+ years of hands-on analog IC design experience. Strong CMOS skills, detailed SerDes sub-circuit design experience and SPICE simulation expertise are required.

  SPICE simulators, Verilog-A, schematic entry tools, physical layout tools, MATLAB, Python

  18d

  Principal Analog Design Engineer-19318

  Markham, ON

  S

  Synopsys

  6+ YOECandidates need a PhD with 6+ years or a Master's with 8+ years of analog and mixed-signal IC design experience, including FinFET circuit design. Strong transistor-level CMOS and SPICE simulation skills are required.

  Spectre, HSPICE, Verilog-A, schematic entry tools, Python, Perl

  19d

  Analog Design, Architect - 18618

  Mississauga, ON

  S

  Synopsys

  10+ YOECandidates need a PhD with 10+ years or MSc with 12+ years of SerDes or high-speed analog design experience. Synopsys expects silicon-proven TX, RX and clock circuit work, transistor-level CMOS and FinFET layout skills, and some leadership of small teams.

  SPICE, Verilog-A, TCL, Perl, C, Python

  29d

  Analog Design, Manager - 18463

  Kanata, ON

  S

  Synopsys

  8+ YOE2+ MgmtCandidates need an M.A.Sc. with 8+ years or a PhD with 6+ years of analog or mixed-signal IC design experience, plus 2+ years of people management. They must have deep Multi-Gbps SerDes expertise, transistor-level design skills, and experience with SPICE, Verilog-A and layout.

  SPICE, Verilog-A, Industry-standard simulation tools

• 6d

  Analog Engineer, Staff

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  4+ YOECandidates need a bachelor's, master's or PhD in electrical engineering with analog or mixed-signal CMOS design experience and several years of ASIC design or verification work. Experience with circuit design tools, transistor-level design, layout optimization and silicon-proven analog blocks is required.

  Cadence ADE, MATLAB, SPICE, Verilog-A, Verilog, VHDL

  8d

  Analog Engineer, Principal

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  8+ YOECandidates need a Master's or PhD in electrical engineering (or a Bachelor's with 2+ years of analog or mixed-signal design), plus 8+ years of ASIC design or related work and silicon-proven analog circuit experience in advanced CMOS. Strong skills in Cadence, SPICE, MATLAB or Verilog-A are expected.

  Cadence ADE, MATLAB, SPICE, Verilog-A

• 24d

  Sr. Engineer, Staff Analog Design

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  10+ YOECandidates need a Master's or PhD in Electrical Engineering, 10+ years in analog/mixed-signal CMOS design, and PLL design experience. Cadence tools and lab characterization experience are also required.

  Cadence, SystemVerilog, Verilog-A

  24d

  Engineer, Staff Analog Design

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  6+ YOECandidates need a Master's or PhD in Electrical Engineering and 6+ years of analog or mixed-signal IC design, including PLL design, CMOS or BiCMOS experience, and hands-on lab characterization.

  Cadence, SystemVerilog, Verilog-A, AMS

• 24d

  Analog IC Design Engineer

  Toronto, ON

  T

  Talentlab

  5+ YOECandidates need an MSc or PhD in electrical engineering or a related field and 5+ years of analog IC design experience, preferably silicon-proven. They need hands-on advanced CMOS experience, SPICE and Verilog-A simulation skills, and EDA tool proficiency.

  SPICE, Verilog-A, EDA tools

• 25d

  Analog Mixed Signal Engineer Intern (Toronto)

  Toronto, ON

  $55–$70/hr

  AL

  Astera Labs Early Career - North America 2027

  Astera Labs needs candidates pursuing an M.S. or Ph.D. in Electrical Engineering, ideally with prior analog, mixed-signal, RF or custom IC design internship experience. Strong circuit fundamentals, device physics and simulation skills are expected.

  Industry-standard circuit design and simulation tools, Verilog-A, Verilog, Python, MATLAB

• 1mo

  System Architect Verification Engineer

  Ottawa, ON

  On-siteFull Time

  R

  Ranovus

  6+ YOECandidates need a Bachelor's in Electrical Engineering or related field with 6+ years, or a PhD with 3+ years, in digital or mixed-signal verification using SystemVerilog. Familiarity with RTL simulation tools, closed-loop control, photonic components and Python or MATLAB is also required.

  SystemVerilog, Verilog-A, Verilog-AMS, SPICE, Python, MATLAB

• 1mo

  Principal Engineer - Analog Design

  Ottawa, ON

  $107k–$157k/yrFull Time

  MC

  Microchip - Canada

  5+ YOECandidates need a Master's or PhD in electrical engineering and at least 5 years of analog and mixed-signal circuit experience. Microchip Technology prefers experience with ADCs, DACs, filters, PLLs, DLLs and high-speed I/Os, plus scripting in SKILL, Python, Perl or Tcl.

  Cadence, Verilog-A, SKILL, Python, Perl, Tcl

  1mo

  Principal Engineer - Analog Design

  Toronto, ON +1

  $107k–$157k/yrFull Time

  MC

  Microchip - Canada

  5+ YOECandidates need a Master's or PhD in electrical engineering and at least 5 years of analog and mixed-signal circuit experience. Microchip Technology prefers experience with ADCs, DACs, filters, PLLs, DLLs and high-speed I/Os, plus scripting in SKILL, Python, Perl or Tcl.

  Cadence, Verilog-A, SKILL, Python, Perl, Tcl

  1mo

  Ingénieur principal en analogique/ Principal Engineer - Analog Design

  Montréal, QC

  Full Time

  MC

  Microchip - Canada

  5+ YOECandidates need a master's or PhD in electrical engineering and at least 5 years of analog and mixed-signal design experience. Strong skills in high-speed circuits, Cadence IC tools, scripting and Verilog-A are expected.

  Cadence IC, Verilog-A, Skill, Python, Perl, Tcl

• 1mo

  Senior Engineer - Analog Design

  Ottawa, ON

  Full Time

  MS

  MCHP Semiconductor Canada ULC

  3+ YOECandidates need a Master's or PhD in Electrical Engineering and about 3 to 5 years of analog or mixed-signal IC design experience. They should know PLLs, ADCs, filters or high-speed I/O and use Cadence IC design tools.

  Cadence IC design tools, Verilog-A, Skill, Python, Perl, Tcl

  1mo

  Senior Technical Staff Engineer - Analog Design

  Ottawa, ON

  Full Time

  MS

  MCHP Semiconductor Canada ULC

  10+ YOECandidates need a Master's or Doctorate in Electrical Engineering or a related field and 10+ years of analog and mixed-signal IC design experience, including PLLs, DLLs, ADCs, DACs and high-speed I/O. Strong skills in Cadence tools, scripting and multi-site teamwork are required.

  Cadence, Verilog-A, Skill, Python, Perl, Tcl

  1mo

  Ingénieur principal du personnel technique – Conception analogique/ Senior Technical Staff Engineer - Analog Design

  Montréal, QC

  Full Time

  MS

  MCHP Semiconductor Canada ULC

  10+ YOEMaîtrise ou doctorat en génie électrique; Plus de 10 ans d’expérience en circuits intégrés analogiques et mixtes; Expérience en PLL/DLL, ADC/DAC et interfaces E/S haute vitesse

  Cadence IC, Verilog-A, Skill, Python, Perl, Tcl

• 1mo

  Analog/Mixed Signal Architect

  Toronto, ON

  

  Lightmatter

  Candidates need a PhD in electrical engineering, physics, applied physics or a related analog discipline, plus experience designing optical receivers and transmitters in advanced CMOS. Strong simulation skills in Cadence Virtuoso and Spectre, clear written communication and problem-solving on open-ended problems are also required.

  Cadence Virtuoso, Cadence Spectre, Verilog-A, IBIS-AMI

9 companies