As of November 6, 2026, Jobsy lists 9 rtl design engineer jobs in Canada. The most active employers are Advanced Micro Devices, Inc, AMD, Inc. and Mercor. Skills often requested: rtl, attention to detail, perl and python.
No matching filters. Try another name.
9 jobs·Latest jobs · Canada··
Why we group jobs by company
Jobs from the same identified company share one card in each results page. As you load more, we merge that company’s additional jobs into its existing card, so large employers do not keep taking extra space. Use the arrows or numbered dots to browse, or View all to compare its loaded jobs and reach the company’s full list. Company pages show separate job cards.
Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong Verilog and SystemVerilog skills, scripting experience, and knowledge of AXI, AHB and AMBA protocols. Experience with ASIC design flows and processor or security subsystems is preferred.
Candidates need a bachelor's or master's degree in electrical or computer engineering or a related field, with strong Verilog and SystemVerilog skills and knowledge of CPU and embedded processor architectures. Experience with AXI, AHB, AMBA and ASIC design tools is preferred.
Candidates need a Bachelor's or Master's degree in Electrical or Computer Engineering or Computer Science (Master's preferred), plus proven RTL design and verification experience. Strong Verilog, SystemVerilog, scripting, and bus protocol knowledge (AXI, AHB, AMBA) are expected.
Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. Strong analytical, communication and teamwork skills are expected, along with scripting in Python or Perl.
RTL, DFT, Firmware, Analytical skills, Problem solving, Attention to detail
AMD needs candidates with a Bachelor's or Master's degree in an electrical, computer or related engineering field, with Master's preferred. Strong skills in Verilog, SystemVerilog and scripting such as Python, Tcl or Perl are expected, along with knowledge of processor subsystems and ASIC design flows.
Candidates need a strong background in RTL design, Verilog and SystemVerilog, and scripting in Python, Tcl, Perl, Ruby, or Make. Experience with AXI, AHB, AMBA protocols, ASIC design tools, and a Bachelor's or Master's degree in electrical or computer engineering are expected.
Verilog, SystemVerilog, C-DPI, FPGA, ASIC simulation and synthesis tools
Candidates need a Bachelor's or Master's degree in electrical or computer engineering, computer science or a related field, with Verilog and SystemVerilog skills, scripting experience, and knowledge of bus protocols such as AXI and AHB. Experience with ASIC design tools and CPU or microprocessor subsystem architecture is preferred.
Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. A bachelor's or master's degree in electrical engineering or equivalent is preferred.
3+ YOECandidates need 3 to 10 years of digital RTL design or design verification experience, strong Verilog, SystemVerilog and UVM skills, and solid digital design fundamentals. Experience with ASIC design flows and EDA tools is also required.