Senior SoC Design Engineer
Burnaby, BCMCHP Semiconductor Canada ULC
3+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.
Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl
Technical Staff Engineer - Signal Integrity
Ottawa, ONMCHP Semiconductor Canada ULC
12+ YOECandidates need a bachelor's degree in electronics engineering and 12 or more years of signal integrity design experience. Strong skills with field solvers, circuit simulators, transmission line theory and lab measurement equipment are required.
HFSS, CST MWS, SIWave, ADS, Spectre, HSPICE
Senior Engineer - Analog Design
Ottawa, ONMCHP Semiconductor Canada ULC
3+ YOECandidates need a Master's or PhD in Electrical Engineering and about 3 to 5 years of analog or mixed-signal IC design experience. They should know PLLs, ADCs, filters or high-speed I/O and use Cadence IC design tools.
Cadence IC design tools, Verilog-A, Skill, Python, Perl, Tcl
Senior Technical Staff Engineer - Analog Design
Ottawa, ONMCHP Semiconductor Canada ULC
10+ YOECandidates need a Master's or Doctorate in Electrical Engineering or a related field and 10+ years of analog and mixed-signal IC design experience, including PLLs, DLLs, ADCs, DACs and high-speed I/O. Strong skills in Cadence tools, scripting and multi-site teamwork are required.
Cadence, Verilog-A, Skill, Python, Perl, Tcl
Ingénieur principal du personnel technique – Conception analogique/ Senior Technical Staff Engineer - Analog Design
Montréal, QCMCHP Semiconductor Canada ULC
10+ YOEMaîtrise ou doctorat en génie électrique; Plus de 10 ans d’expérience en circuits intégrés analogiques et mixtes; Expérience en PLL/DLL, ADC/DAC et interfaces E/S haute vitesse
Cadence IC, Verilog-A, Skill, Python, Perl, Tcl