Senior FPGA Engineer (Hybrid)
Burnaby, BCKardium Inc.
5+ YOECandidates need a bachelor's degree or higher in an engineering field and at least 5 years of FPGA development and verification experience. They need strong VHDL skills, experience with Vivado and Active-HDL, and knowledge of timing closure, AXI interfaces and clock domain crossing.
Vivado, Active-HDL, logic analyzer, oscilloscope, Git, Aldec ALINT