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Positron AI
8+ YOEPositron AI needs 8+ years of ASIC development with several production tapeouts, deep DFT experience, and hands-on Siemens Tessent. Candidates also need Verilog/SystemVerilog RTL skills, synthesis and gate-level verification, and scripting in Python, Tcl or Perl.
Siemens Tessent, Verilog, SystemVerilog, Python, Tcl, Perl
Collabera
3+ YOECandidates need commercial firmware experience in neural network processing or machine learning, plus compiler and optimization experience. Strong C/C++ skills and embedded multiprocessor experience are required, along with debugging skills using JTAG.
JTAG, FPGA, Caffe, schematics
onsemi: With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety,…
3+ YOECandidates need a Bachelor's or Master's degree in an engineering discipline and 3-5 years of embedded firmware experience. Strong embedded C, microprocessor and communication protocol knowledge (UART, I2C, SPI, USB) and experience with AI-assisted development tools are required.
Git, JIRA, FPGA, oscilloscope, logic analyzer, hardware debugger
Qualcomm Canada ULC
8+ YOECandidates need an engineering or computer science degree plus 8+ years of software engineering experience, or a master's with 7+ years. They also need 4+ years coding in C, C++, Java or Python, strong embedded firmware and lab debug skills, and team leadership experience.
Git, Python, RISC-V
Qualcomm Canada ULC
6+ YOECandidates need an engineering or computer science degree and 4 to 6+ years of software engineering experience, depending on degree level. They also need at least 3 years of programming experience in languages such as C, C++, Java or Python.
JTAG debuggers, git, Verilog, SystemVerilog
BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.
10+ YOECandidates need 10 or more years of hands-on ASIC verification experience through tape-out sign-off, strong SystemVerilog and UVM skills, and experience with high-speed interfaces or die-to-die interconnect. Scripting, regression automation and clear written communication are essential.
SystemVerilog, UVM, UPF
Rambus: As an industry pioneer with over 30 years experience, Rambus is a premier provider of chips & silicon IP.
8+ YOECandidates need a BS, MS or PhD in electrical or computer engineering, 8+ years of ASIC/SoC logic design experience, and expert SystemVerilog skills. Experience with synthesis, timing closure and PCIe Gen5/Gen6/Gen7 is preferred.
SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, SpyGlass, Questa
SiFive, Inc.
Candidates need experience with concurrency-sensitive upstream Linux kernel code, debugging hardware and software bugs in CPUs and SoCs, and working with CPU architects. They also need experience with Linux on FPGA or emulation, hypervisors, and familiarity with the RISC-V architecture.
Linux kernel, OpenSBI, hardware debuggers, FPGA, emulation platforms
Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.
Candidates need deep knowledge of computer architecture and chip microarchitecture, plus hands-on RTL design in Verilog or VHDL and familiarity with full ASIC flows. Experience optimizing for power, performance and area, and working collaboratively on specifications and design reviews, is needed. Prior work on on-chip fabric or interconnect design is an asset.
Verilog, VHDL, FPGA, UVM, emulation platforms
15 companies