Principal Design Verification Engineer
Toronto, ONindie
7+ YOECandidates need a BSEE, BSCE or BSCS and 7+ years of design verification experience. Required skills include constrained random verification with SystemVerilog and UVM, coverage-driven verification, and strong programming in C/C++ with Python, Tcl or Perl scripting.
SystemVerilog, UVM, C, C++, Python, Tcl