“Cadence simulation tools” jobs in Canada – Page 3

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• 1mo

  Hardware Designer

  Remote in Canada

  $95k–$145k/yrRemoteFull Time

  

  Fidus Systems: Founded in 2001, Fidus Systems is a premier electronic system design and development company with specialized expertise in FPGA design, embedded…

  5+ YOECandidates need at least 5 years of electronics design experience and a degree in electrical or computer engineering. Strong knowledge of high-speed circuits, multi-layer PCB design and high-speed protocols such as PCIe, DDR4 and USB-C is required.

  OrCAD Capture CIS, Cadence Allegro, LTSpice, oscilloscope, VNA, signal generator

  1mo

  Signal Integrity and Power Integrity Designer

  Remote in Canada

  $105k–$155k/yrRemote

  

  Fidus Systems: Founded in 2001, Fidus Systems is a premier electronic system design and development company with specialized expertise in FPGA design, embedded…

  5+ YOECandidates need an MS or PhD in electrical engineering and five or more years designing high-speed circuits or RF structures. Fidus Systems also requires hands-on DDR and SERDES experience, proficiency with Sigrity, HSPICE, ADS, HFSS and Hyperlynx, and lab skills with TDR, network analyzers and oscilloscopes.

  Cadence Sigrity, HSPICE, ADS, HFSS, Hyperlynx, TDR

• 1mo

  Principal SI/PI Engineer - 18619

  Mississauga, ON

  S

  Synopsys

  12+ YOECandidates need a bachelor's degree (master's or PhD preferred) in electrical engineering and 12+ years of high-speed SI/PI experience on SerDes links. They also need strong skills in simulation tools, lab measurement and scripting, plus proven technical leadership.

  HSPICE, Keysight ADS, SystemVue, Ansys HFSS, SIwave, AEDT

  1mo

  Hardware Validation Engineer, Sr Staff

  Nepean, ON

  S

  Synopsys

  6+ YOECandidates need 6-8+ years of high-speed hardware design and validation experience and expert Cadence Allegro skills. They also need strong signal integrity knowledge, bench debugging experience and familiarity with JTAG, I2C, SPI and UART interfaces.

  Cadence Allegro, logic analyzer, oscilloscope, VNA, spectrum analyzer, protocol analyzer

• 1mo

  DFT Engineer, Principal

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  8+ YOECandidates need 10+ years of SoC experience in RTL, DFT or front-end roles, and extensive use of Siemens, Synopsys and Cadence DFT tools. Strong Verilog, VHDL and SystemVerilog skills, knowledge of JTAG, iJTAG and BIST standards, and TCL or Python scripting are expected.

  Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL

  1mo

  DFT Engineer (Senior to Staff level)

  Toronto, ON

  On-site

  

  Qualcomm Canada ULC

  10+ YOECandidates need a bachelor's degree in an engineering or computer science field and 10+ years of SoC design experience in RTL, DFT or front-end work. They need strong knowledge of DFT tools, Verilog, VHDL and SystemVerilog, and standards such as JTAG, iJTAG and BIST.

  Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL

  1mo

  Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)

  Markham, ON

  On-site

  

  Qualcomm Canada ULC

  2+ YOECandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.

  SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools

• 1mo

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in computer or electrical engineering, and strong Verilog or SystemVerilog RTL design skills. Experience delivering ASIC or FPGA products, plus networking or high-speed interface knowledge, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  1mo

  Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need strong SystemVerilog and UVM skills, solid ASIC/SoC verification experience, and familiarity with constrained-random, coverage-driven and formal (SVA) methods. A bachelor's or master's in computer or electrical engineering is required.

  Synopsys VCS, Cadence IES, Cadence IEV, Jasper, VC-Formal, Magellan

• 1mo

  Analog/mixed-signal IC Developer - Acacia (Hybrid)

  Kanata, ON +1

  Full Time

  

  Cisco

  8+ YOECandidates need a bachelor's with 8 years, a master's with 6, or a PhD with 3 years of related experience, plus hands-on design, simulation and measurement of high-speed ICs in at least three areas such as SerDes, PLLs, output drivers, clock distribution, amplifiers and equalization.

  Cadence Virtuoso, Spectre, Calibre, EMX, Matlab

  1mo

  Senior Mixed-Signal Designer - Acacia (Hybrid)

  Kanata, ON

  Full Time

  

  Cisco

  5+ YOECandidates need a degree plus 5 to 12 years of related experience, depending on the degree level, and experience designing, simulating and measuring high-speed ICs across at least three of: SerDes, output drivers, PLLs, clock distribution, op-amps/PGAs or equalization. Experience with FinFET, layout and design tools is preferred.

  Cadence Virtuoso, Spectre/APS/SpectreX, Calibre, EMX, Matlab

  1mo

  Principal Analog/mixed-signal IC Developer - Acacia (Hybrid)

  Kanata, ON

  Full Time

  

  Cisco

  7+ YOECandidates need a Bachelor's with 15 years, a Master's with 10 years, or a PhD with 7 years of related experience. They must have high-speed IC design experience in at least three areas and have led a high-performance circuit team.

  Cadence Virtuoso, Calibre, EMX, Matlab

  1mo

  Senior Analog/mixed-signal IC Designer - Acacia (Hybrid)

  Kanata, ON

  Full Time

  

  Cisco

  12+ YOECisco candidates need 12+ years of experience with a BSEE, 8+ with an MS, or 5+ with a PhD. Experience in high-speed IC design in at least three areas such as SerDes, PLLs, output drivers, equalization and amplifiers is required.

  Cadence Virtuoso, Spectre, Calibre, EMX, Matlab

  1mo

  Senior Analog/mixed-signal IC Developer - Acacia - (Hybrid)

  Kanata, ON +1

  Full Time

  

  Cisco

  12+ YOECandidates need a BSEE with 12+ years of experience, or an equivalent MS or PhD background, plus hands-on design, simulation and measurement of high-speed ICs in at least three areas such as serial links, PLLs, drivers and data converters. Experience with FinFET technology, high-speed layout and Cadence Virtuoso is a plus.

  Cadence Virtuoso, Spectre, SpectreX, APS, Matlab, EMX

• 1mo

  Software Manager, MachineLogic / Gestionnaire, génie logiciel (MachineLogic)

  Montréal, QC

  Full Time

  

  Vention

  8+ YOE2+ Mgmt8+ années d'expérience en développement logiciel; 2+ années en gestion ou leadership technique d'une équipe; Expérience avec les systèmes basés sur les LLM ou agents

  Python, TypeScript, MachineMotion, Fanuc CRX

  1mo

  VP Product — Software Platform / VP Produit — Plateforme Logicielle

  Montréal, QC

  Full Time

  

  Vention

  12+ YOE12 ans et plus d'expérience en leadership produit ou technologique; Gestion de plusieurs équipes produit; Solide compréhension de l'architecture logicielle, des API et des systèmes embarqués

  Robotics, Embedded systems, Lead a team, Procurement, Leadership, Prioritization

• 1mo

  ASIC Verification Engineer (7745)

  Ottawa, ON

  T

  TSMC

  5+ YOECandidates need a master's or PhD in electrical or computer engineering and 5-10 years of digital verification experience. They should be strong in SystemVerilog, UVM, assertions, Unix/Linux and EDA tools such as VCS or Incisive.

  Synopsys VCS, Cadence Incisive, UVM, Unix/Linux

• 1mo

  SMTS Logic Design

  Montréal, QC

  

  Rambus: As an industry pioneer with over 30 years experience, Rambus is a premier provider of chips & silicon IP.

  8+ YOECandidates need a BS, MS or PhD in electrical or computer engineering, 8+ years of ASIC/SoC logic design experience, and expert SystemVerilog skills. Experience with synthesis, timing closure and PCIe Gen5/Gen6/Gen7 is preferred.

  SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, SpyGlass, Questa

• 1mo

  Gestionnaire sénior: Chef de l'intégration des capacités d'affaire / Senior Manager - Head of Business Capabilities Integration

  Montréal, QC

  Full Time

  AC

  Airbus Canada Limited Partnership

  15+ YOEPlus de 15 ans d'expérience en transformation aéronautique ou industrielle; Expérience du déploiement du fil numérique (PLM, ERP, MES); Expérience en double ligne hiérarchique et leadership matriciel

  PLM, ERP, MES

• 1mo

  Analog Engineer Intern - PhD

  Ottawa, ON

  Full Time

  MS

  Marvell Semiconductor Canada Inc. (MSCI)

  Candidates need a master's degree in electrical engineering or a related field, strong circuit design knowledge, transistor-level design skills, and an understanding of device physics and stability analysis. Experience with Cadence Virtuoso or Mentor Custom Compiler is preferred.

  Cadence Virtuoso, Mentor Custom Compiler

  1mo

  Analog Engineer Intern - PhD

  Vancouver, BC

  Full Time

  MS

  Marvell Semiconductor Canada Inc. (MSCI)

  Candidates need to be currently pursuing a PhD or MS in electrical engineering or a related technical field. They need strong analog circuit design knowledge, transistor-level design skills, device physics understanding, feedback and loop stability analysis, and good communication and documentation skills.

  Cadence Virtuoso

• 1mo

  Firmware Design Engineer

  Mount Royal, SK

  $74k/yrFull Time

  C

  Cadence

  Solide programmation en C/C++ et Python; Compréhension des principes de communication filaire; Connaissance des circuits mixtes et du traitement numérique du signal

  Firmware, Work independently, Leadership, C, C++, Python

  1mo

  Analog CAD Engineering specialist

  Mount Royal, SK +5

  Full Time

  C

  Cadence

  Candidates need a BSEE or MSEE, prior experience in analog CAD support, and a strong understanding of circuit and layout design. Excellent communication, presentation and customer service skills are also required.

  Cadence Virtuoso, Cadence Pegasus, Cadence Quantus, Cadence Composer Schematic, Virtuoso Layout

  1mo

  Ingénieur en conception de micrologiciel - Firmware Design Engineer

  Mount Royal, SK

  $74k/yrFull Time

  C

  Cadence

  Programmation solide en C/C++ et Python; Connaissance des communications filaires; Connaissance de la conception de circuits mixtes et du traitement numérique du signal

  Firmware, Work independently, Leadership, C, C++, Python

11 companies