FPGA Design Engineer
Nepean, ONActalent: Actalent is an operating company of Allegis Group, the global leader in talent solutions.
5+ YOECandidates need 5+ years of ASIC or FPGA design experience, strong SystemVerilog skills, and hands-on Cadence simulation and design debug experience. Experience with synthesis, timing analysis and simulation frameworks is also required.
Xilinx Vivado, Cadence simulation tools, SystemVerilog, VHDL
FPGA Design Engineer
Ottawa, ONActalent: Actalent is an operating company of Allegis Group, the global leader in talent solutions.
5+ YOECandidates need 5+ years of ASIC/FPGA design experience, strong SystemVerilog skills, hands-on Cadence simulation experience, and practical debug and timing analysis skills. VHDL, Xilinx Vivado, Python, C/C++, DSP and high-speed interface experience are assets.
SystemVerilog, Xilinx, Vivado, Cadence simulation tools, Python, C