Connectivity Project Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ YOE5+ MgmtCandidates need a university degree in science or engineering and 6 to 8+ years of ASIC design or validation experience, depending on degree level. They also need more than 5 years in technical leadership, experience with high-performance SoCs and SerDes, and strong communication skills.
Teamwork, Design hardware, Firmware, Regulatory compliance, Communication skills, Decision making
Design Verification Engineer — Memory Subsystem (Vancouver)
Vancouver, BCQualcomm Canada ULC
3+ YOECandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.
Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers