“Synopsys tools” jobs in Canada – Page 3

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• 22d

  R&D Engineering, Staff Engineer

  Ottawa, ON

  S

  Synopsys

  7+ YOECandidates need 7-8+ years of experience with a bachelor's degree, 5-6+ with a master's, or 3-4+ with a PhD, in an engineering or computer science field. They need strong skills in CAD or simulation infrastructure, scripting in Python, Tcl or Shell, and Linux environments.

  Synopsys EDA design suite, Linux, Python, Tcl, Shell

  23d

  Analog Design, Architect - 18618

  Mississauga, ON

  S

  Synopsys

  10+ YOECandidates need a PhD with 10+ years or MSc with 12+ years of SerDes or high-speed analog design experience. Synopsys expects silicon-proven TX, RX and clock circuit work, transistor-level CMOS and FinFET layout skills, and some leadership of small teams.

  SPICE, Verilog-A, TCL, Perl, C, Python

  27d

  CAD Software Engineer, Principal-18736

  Nepean, ON

  S

  Synopsys

  10+ YOESynopsys needs candidates with an MS or PhD in Computer Science or Electrical Engineering and at least 10 years of industry experience. They should be strong in Python, Perl, TCL, UNIX/Linux, Git, and Perforce, and have hands-on experience with Custom Compiler/Virtuoso.

  Custom Compiler, Virtuoso, Git, Perforce, UNIX, Linux

• 23d

  Sr. Staff Physical Design Engineer

  Vancouver, BC

  Full Time

  AM

  Advanced Micro Devices, Inc

  AMD needs candidates with strong physical design experience for high-performance semiconductors, including timing closure and signoff. Candidates should know tools such as ICC2, Fusion Compiler, PrimeTime, Calibre and Innovus, and be proficient in Python and TCL.

  Synopsys ICC2, Synopsys ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre

• 24d

  Sr. Staff Physical Design Engineer

  Vancouver, BC

  Full Time

  AI

  AMD, Inc.

  Candidates need strong experience in high-performance physical design, timing closure and physical signoff, plus proficiency in Python and TCL for flow automation. Experience leading engineers and an electronics or electrical engineering background are preferred.

  Synopsys ICC2, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache RedHawk

  29d

  Physical Design Engineer

  Vancouver, BC

  Full Time

  AI

  AMD, Inc.

  Candidates need hands-on ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and tape-out experience on advanced nodes such as 3nm, 5nm, 7nm or 16nm. A bachelor's or master's degree in computer or electrical engineering is required.

  Synopsys, Cadence, Mentor Graphics, Verilog

  29d

  SoC Physical Design Implementation Lead

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need deep hands-on experience with place and route, static timing and physical verification on large SoCs, plus advanced-node and 3D stacking knowledge. Scripting in Tcl, Perl or Shell and a bachelor's or master's in electrical or computer engineering are preferred.

  Synopsys, Cadence, Siemens (Mentor Graphics), Tcl, Perl, Shell

  29d

  3D IC and ADVANCED PACKAGING CAD ENGINEER

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a computer or electrical engineering degree, experience in 3D-IC and advanced packaging, and hands-on work with Synopsys or Cadence EDA tools. Strong Python, TCL and Perl scripting on Linux, plus experience applying AI or LLMs to CAD or hardware design, are preferred.

  Synopsys 3DIC Compiler, Synopsys EDA tools, Cadence EDA tools, Verilog, UPF, Python

  29d

  Sr. Manager Packaging Engineering

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need a bachelor's degree or higher in electrical, computer, or mechanical engineering, plus experience leading teams on complex semiconductor package projects. Strong program management, stakeholder communication, and familiarity with high-speed design and advanced packaging are needed.

  Synopsys 3DICC, Cadence SiP, Cadence APD

  29d

  Verification Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need strong SystemVerilog and UVM skills, experience with ASIC or SoC verification, and familiarity with constrained-random, coverage-driven and formal verification. A Bachelor's or Master's in computer or electrical engineering is required.

  UVM, Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal

  29d

  Lead Physical Design Engineer, Place & Route

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need hands-on place-and-route experience on complex or advanced-node designs, proficiency with Synopsys Fusion Compiler, Cadence and Siemens EDA tools, and scripting in TCL, Perl or Shell. A bachelor's or master's degree in electrical or computer engineering is preferred.

  Synopsys Fusion Compiler, Cadence, Siemens EDA, TCL, Perl, Shell

  29d

  Physical Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  8+ YOECandidates need a degree in electrical, electronics or computer engineering, with 8 or more years of physical design experience (or 4 with a master's, or 2 with a PhD). They must have hands-on expertise in place and route, timing closure, physical verification and debugging CAD flows with industry tools such as Synopsys, Cadence and Mentor Graphics.

  Synopsys ICC2, Innovus, PrimeTime, Spyglass, RedHawk, VSI

  29d

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need proven SoC implementation and tapeout experience, in-depth LEC and low power static verification skills, and hands-on use of Formality or Conformal, VC-LP or CLP, and Design Compiler or Fusion Compiler. Verilog, VHDL, UPF, Tcl, Perl and Python skills and a BS/MS in electrical engineering or a related field are also expected.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

  29d

  Physical Design Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need hands-on ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and tape-out experience on advanced nodes such as 3nm, 5nm, 7nm or 16nm. A bachelor's or master's degree in computer or electrical engineering is required.

  Synopsys, Cadence, Mentor Graphics, Verilog

  29d

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

• 24d

  Agentic AI Developer

  Toronto, ON

  Full Time

  EC

  Equifax Canada Co.

  3+ YOECandidates need 3+ years of production AI or ML experience, including LLM orchestration and agent patterns. They need strong Python or TypeScript skills, experience with agent frameworks, RAG and vector databases, and structured JSON outputs. Regulated-industry and UiPath experience are assets.

  LangGraph, Google ADK, UiPath, Vector databases

  28d

  Agentic AI Optimization Developer

  Toronto, ON

  Full Time

  EC

  Equifax Canada Co.

  3+ YOECandidates need 3+ years in software quality engineering, test automation, or data/ML engineering, with recent focus on LLM testing or orchestration. They need strong Python automation skills and experience with JSON schema design for LLM tool-calling.

  Python, TypeScript, LangGraph, Google ADK, Vertex AI, Gemini

• 27d

  Senior Analog Layout Engineer

  Ottawa, ON

  $117k–$187k/yrFull Time

  CC

  Ciena Canada ULC

  Ciena Canada ULC needs a candidate with a bachelor's degree in engineering or science and industrial experience in high-speed analog layout in advanced BiCMOS or CMOS. Candidates must work well alone and in teams, use Cadence, Mentor, and Synopsys tools, and communicate clearly in English.

  Cadence Virtuoso, Calibre PERC, Calibre PEX, Synopsys tools

• 28d

  Principal Engineer, CAD

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  7+ YOECandidates need a BA or BS in electrical engineering, computer science or a related field and at least 7 years of CMOS IC CAD support experience. They must know Cadence, Synopsys and Siemens EDA tools, scripting languages such as SKILL, Python and Tcl, and Linux.

  Cadence Virtuoso, Spectre, Assura, Innovus, Tempus, Synopsys Design Compiler

  28d

  ASIC Digital Verification Engineer

  Ottawa, ON

  

  SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…

  Candidates need knowledge of chip specifications and verification plans, plus SystemVerilog and UVM for digital verification. Experience with Synopsys or Cadence simulators, SystemVerilog assertions, functional and code coverage, and working in Unix/Linux is also needed.

  SystemVerilog, UVM, Unix, Linux

• 28d

  Staff Physical Design Engineer

  Toronto, ON

  T

  Talentlab

  5+ YOECandidates need 5+ years of physical design experience on digital ASICs, including advanced nodes like TSMC N5, N4P or N3. They must know industry EDA tools, PnR, timing analysis and physical verification, and be strong in TCL, Python or Perl.

  Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk, TCL

• 29d

  Ingénieur mécanique Lead, Méthodes et outillages / Lead Mechanical Engineer, Methods and Tooling

  Brossard, QC

  Full Time

  GR

  GE Renewable Energy Canada Inc.

  4+ YOECandidates need a mechanical engineering degree, at least 4 years in a similar role, and experience designing lifting equipment or working on site. They must be OIQ members or able to become one, and be fluent in English and French.

  AutoCAD, SolidWorks, GE PLM

  29d

  Ingénieur mécanique Lead, Méthodes et outillages / Lead Mechanical Engineer, Methods and Tooling

  Brossard, QC

  Full Time

  GR

  GE Renewable Energy Canada Inc.

  4+ YOECandidates need a mechanical engineering degree, at least 4 years in a similar role, and experience designing lifting equipment or working on site. They must be OIQ members or able to become one, and be fluent in English and French.

  AutoCAD, SolidWorks, GE PLM

• 29d

  Ingénieur mécanique Lead, Méthodes et outillages / Lead Mechanical Engineer, Methods and Tooling

  Brossard, QC

  Full Time

  

  GE Vernova: GE Vernova is a purpose-built energy technology company on a mission to electrify to thrive and decarbonize the world.

  5+ YOECandidates need a mechanical engineering bachelor's degree and at least 5 years in a similar role, plus experience designing lifting equipment or access platforms. Membership in the Ordre des ingénieurs du Québec, or the ability to obtain it, is required, along with fluent written and spoken French and English and CAD skills in AutoCAD and SolidWorks.

  AutoCAD, SolidWorks

9 companies