“System Verilog” jobs in Canada – Page 3

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• 10d

  FY27 Intern - Display IP Engineering Internship - Canada (16 months)

  Markham, ON

  On-siteInternship

  

  Qualcomm Canada ULC

  1+ YOECandidates need to be enrolled in a bachelor's program in electrical, computer or engineering science, or a related field, with a graduation date of November 2028 or later. They need programming experience in C, C++ or Python, knowledge of RTL, Verilog or SystemVerilog and digital design, and good communication and teamwork skills.

  Verilog, VHDL, Perl, Python, TCL, GNU Make

  10d

  Staff Verification Engineer, Compute Subsystems

  Markham, ON

  On-site

  

  Qualcomm Canada ULC

  5+ YOECandidates need a bachelor's, master's, or PhD in engineering or science with several years of ASIC design or verification experience, plus strong UVM and SystemVerilog skills, bus protocol knowledge, and scripting in Perl or Python.

  UVM, Perl, Python, C

  10d

  FY27 Intern - Edge AI and Display Hardware Architecture Development Engineering Internship - Canada (16 months)

  Markham, ON

  On-siteInternship

  

  Qualcomm Canada ULC

  Qualcomm Canada ULC needs candidates enrolled in an engineering or computer science bachelor's program, available May/June 2027 to August/September 2028 and graduating November 2028 or later. Strong analytical skills, programming in C/C++ or Python, and HW modeling and simulation experience are required.

  Verilog, VHDL, C/C++, Python, HW simulation tools, HW CAD tools

  11d

  FY27 Intern - Camera HW ASIC Verification Intern - Canada (12 or 16 months)

  Vancouver, BC

  On-siteInternship

  

  Qualcomm Canada ULC

  1+ YOECandidates need Verilog or SystemVerilog skills, ASIC design verification experience and scripting ability. Study toward a bachelor's degree in electrical, computer or a related engineering field is required.

  Verilog, UVM, Python, Perl

  11d

  FY27 Intern - Camera Design Engineering Internship - Canada (12 or 16 months)

  Vancouver, BC

  On-siteInternship

  

  Qualcomm Canada ULC

  1+ YOECandidates need to be enrolled toward a bachelor's degree in electrical, computer or a related engineering or science field. They need experience in Tcl, Perl, Python and SystemVerilog, plus academic or project VLSI experience as an asset.

  Verilog, Tcl, Perl, Python, EDA tools

  11d

  Camera Design Engineer

  Vancouver, BC

  On-site

  

  Qualcomm Canada ULC

  3+ YOECandidates need a bachelor's, master's or PhD in a computer, electrical or related engineering field, with 4 to 2 years of hardware or related experience depending on degree. Verilog or VHDL RTL design, design verification and bus protocol experience are key.

  Verilog, VHDL, TCL, Perl, Python

• 11d

  Emulation Performance/Debug Engineer

  Markham, ON

  On-site

  QT

  Qualcomm Technologies, Inc.

  2+ YOECandidates need a bachelor's degree in science or engineering with 2+ years of ASIC work, or a master's with 1+ year. Experience with emulation platforms, Verilog/SystemVerilog, C, Python, TCL and FPGA timing closure is preferred.

  Veloce, Palladium, Xilinx FPGA, Intel FPGA, JTAG, Python

  11d

  SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)

  Markham, ON

  On-site

  QT

  Qualcomm Technologies, Inc.

  5+ YOEQualcomm Technologies needs candidates with a bachelor's degree in engineering and 5+ years in SoC validation or related areas. They must know clock or power validation, C and Python, lab instruments such as oscilloscopes, and JTAG debug on ARM-based SoCs.

  Oscilloscope, Logic analyzer, Multimeter, Python, C, Perl

  11d

  EDA/CAD Software Engineer, Staff

  Markham, ON

  On-site

  QT

  Qualcomm Technologies, Inc.

  7+ YOECandidates need a bachelor's degree in science or engineering with 7+ years of related experience, or the equivalent advanced degree with fewer years. Strong C++, Linux, CAD software development and VLSI or ASIC design skills are preferred.

  Git, LSF, JIRA, GCC

  11d

  System Validation Lead, Staff (AI Accelerator Platform)

  Markham, ON

  On-site

  QT

  Qualcomm Technologies, Inc.

  8+ YOECandidates need 8+ years of silicon validation or platform bring-up experience, strong C and Assembly skills, and bare-metal embedded knowledge. A BS, MS or PhD in an engineering or computer science field is required, plus the minimum years of ASIC work listed for each degree.

  FPGA, Verilog, VHDL, Python, Linux shell, development boards

• 12d

  Sr Manager or Principal Engineer for Firmware Development - 19315

  Markham, ON

  S

  Synopsys

  10+ YOECandidates need a Bachelor's, Master's or PhD in computer or electrical engineering, or equivalent experience, with 10+ years in a related field. They need strong skills in digital logic and firmware development, proficiency in C, Verilog and SystemVerilog/UVM, and experience leading complex projects.

  Verilog, UVM, C, Python, Perl, Bash

  13d

  ASIC Digital Design, Sr Staff Engineer-19314

  Markham, ON

  S

  Synopsys

  8+ YOECandidates need a BS or MS in electronics or electrical engineering with 8+ years of digital verification experience in VMM or UVM. Strong Verilog and SystemVerilog testbench skills, debugging ability, and familiarity with Python or Perl are required.

  Verilog, SystemVerilog, UVM, VMM, Jira, Confluence

• 12d

  Engineering Student - FPGA Designer - Winter 2027

  Sainte-Anne-de-Bellevue, QC

  Full Time

  

  MDA

  MDA Space needs candidates who have completed third year of an electrical or computer engineering degree with at least 3.2/4.0. Experience with VHDL, Verilog, Python or C/C++ and tools like Linux, Git and Jira is an asset, as is French and English.

  VHDL, Verilog, SystemVerilog, Tcl, Python, C/C++

  12d

  Engineering Student - FPGA Verification - Winter 2027

  Sainte-Anne-de-Bellevue, QC

  Full Time

  

  MDA

  Candidates need completion of a third year of an electrical or computer engineering bachelor's degree with a 3.2/4.0 minimum GPA. They need a desire to learn, initiative, and a collaborative attitude, plus security clearance eligibility.

  SystemVerilog, VHDL, Verilog, Tcl, Python, C/C++

• 13d

  Software Engineer - Factory Apps - Intern

  Toronto, ON

  Full Time

  AS

  Altera Semiconductor Technology Canada ULC

  Candidates need to be pursuing a bachelor's degree in computer science, electrical or computer engineering, or a related field. They need C/C++ experience and basic knowledge of digital logic and FPGA or ASIC concepts.

  C/C++, Python, Git, Linux, Verilog, VHDL

• 13d

  Lead Emulation Test Engineer

  Remote in Canada

  RemoteFull Time

  

  Positron AI

  8+ YOECandidates need 8+ years in ASIC emulation or verification, including large Palladium installations, and a BS or MS in electrical engineering, computer engineering or computer science. Strong skills in SystemVerilog, Verilog, C/C++, Python, Tcl and Bash are required, along with knowledge of PCIe, DDR and AXI protocols.

  Cadence Palladium, Verdi, SimVision

• 15d

  Intermediate Electrical Designer/Engineer

  Concord, ON

  Full Time

  D

  Danaher

  3+ YOECandidates need a bachelor's degree in electrical or electronics engineering, at least 3 years of analog, digital and switched mode power supply design experience, and hands-on PCBA testing skills. Schematic entry tools, lab instruments and simulation software are also required.

  Viewdraw, OrCAD, oscilloscope, logic analyzer, protocol analyzer

• 15d

  Intermediate Electrical Designer/Engineer

  Concord, ON

  Full Time

  AS

  AB Sciex LP

  3+ YOECandidates need a bachelor's degree in electrical or electronics engineering or applied science, plus at least 3 years of analog, digital and switched mode power supply design. They also need schematic entry tool experience, PCBA testing skills, and proficiency with lab equipment and simulation software.

  Viewdraw, OrCAD, Oscilloscopes, Protocol analyzers, Logic analyzers

• 15d

  Pre-Si Validation Engineer

  Toronto, ON

  Full Time

  

  Intel Corporation

  6+ YOECandidates need a Bachelor's degree in electrical or computer engineering, 6+ years with formal verification tools and methods, SystemVerilog, and CPU architecture including cache coherence and CXL. Strong problem-solving and communication skills are expected.

  formal verification tools

• 16d

  Staff SoC Design Engineer

  Remote in Canada

  RemoteFull Time

  

  quadric

  5+ YOECandidates need a BS, MS or PhD in electrical or computer engineering, at least 5 years of SoC or ASIC front-end design, and fluency in SystemVerilog or Verilog. Strong computer architecture and low-power design skills are required.

  SystemVerilog, Verilog, VCS, NoC, PCIe, UCIe

• 16d

  Logic Design Engineer

  Kanata, ON

  $72k–$99k/yrFull Time

  NC

  NXP Canada Inc.

  Candidates need a Bachelor's degree in Computer Science, Engineering or a related field, plus knowledge of Verilog RTL design, logic synthesis and timing closure. Experience with complex digital IP, networking protocols and strong teamwork and communication skills are desirable.

  Verilog, logic synthesis tools, Lint, CDC tools, LEC tools

• 19d

  RTL Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong Verilog and SystemVerilog skills, scripting experience, and knowledge of AXI, AHB and AMBA protocols. Experience with ASIC design flows and processor or security subsystems is preferred.

  Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

• 19d

  Senior Embedded Software Designer (6+ month Contract)

  Remote in Canada

  RemoteFull Time, Contract

  

  Kepler Communications

  6+ YOECandidates need 6+ years of embedded software experience on high-reliability systems and a bachelor's degree or equivalent practical experience. They must know C/C++, embedded Linux or RTOS, device drivers, and automated testing, and be willing to use AI-assisted engineering tools.

  Git, Yocto, OpenEmbedded, FreeRTOS, SPI, I2C

  19d

  FPGA Digital Design Engineer (6+ month Contract)

  Toronto, ON

  RemoteFull Time, Contract

  

  Kepler Communications

  5+ YOECandidates need a bachelor's degree in computer or electrical engineering, 5+ years of FPGA/RTL design experience, and skill in Verilog, SystemVerilog or VHDL. They also need Xilinx Zynq or UltraScale experience, timing and clock domain crossing knowledge, and scripting skills.

  Vivado, Quartus, ModelSim, Python, Tcl

13 companies