System Architect Verification Engineer
Ottawa, ONOn-siteFull Time
R
Ranovus
6+ YOECandidates need a Bachelor's in Electrical Engineering or related field with 6+ years, or a PhD with 3+ years, in digital or mixed-signal verification using SystemVerilog. Familiarity with RTL simulation tools, closed-loop control, photonic components and Python or MATLAB is also required.
SystemVerilog, Verilog-A, Verilog-AMS, SPICE, Python, MATLAB