Senior ASIC RTL Design Engineer, AI Networking IP
Ottawa, ONAMD, Inc.
Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.
Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python
Software Engineer, AI & Engineering Productivity Tools
Markham, ONAMD, Inc.
Candidates need production software experience, frontend skills in React, Angular or Vue, and database experience with PostgreSQL, MySQL or MongoDB. AMD also wants proficiency with AI-assisted development tools like Claude Code or Codex and familiarity with Linux environments.
Claude Code, OpenAI Codex, Git, Linux
Sr. Manager - RTL Design Manager
Markham, ONAMD, Inc.
AMD needs a leader with experience managing IP or RTL design teams and strong Verilog/SystemVerilog skills. Candidates should know RTL microarchitecture, ASIC verification flows and on-chip protocols such as AXI and AHB, and hold a bachelor's degree in an engineering or computer discipline.
Verilog, SystemVerilog
Senior Firmware Engineer
Markham, ONAMD, Inc.
Candidates need extensive experience with microcontrollers and embedded C or assembly, strong low-level hardware and firmware interface knowledge, and a bachelor's or master's degree in electronics, computer engineering or another applied science.
Git, GitHub Actions, Python, RTOS, emulation platforms, RTL simulation tools
Design Verification Lead
Markham, ONAMD, Inc.
Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.
SystemVerilog, Verilog, UVM, Python, Perl