FY27 Intern - Soft IP ASIC Engineering Internship - Canada (12 or 16 months)
Ottawa, ONQualcomm Canada ULC
1+ YOEQualcomm Canada needs candidates studying toward a bachelor's degree in electrical, computer or engineering science, or computer science. They need scripting experience in Python, Perl, TCL or Unix/Linux shell, plus source control experience with SVN, CVS or RCS.
Verilog, SystemVerilog, UVM, SVN, CVS, RCS
FY27 Intern - Softip Engineering Co-Op - Canada (4 months)
Ottawa, ONQualcomm Canada ULC
1+ YOECandidates need to be enrolled in a bachelor's or master's program in electrical, computer or related engineering, with scripting experience in Python, Perl, TCL or Unix/Linux shell and experience with source code revision systems.
Verilog, SystemVerilog, UVM, VHDL, SVN, CVS
FY27 Intern - Silicon Validation Internship - Canada (16 months)
Toronto, ONQualcomm Canada ULC
1+ YOEQualcomm Canada needs students in an engineering or computer science bachelor's program, available May/June 2027 to August/September 2028, with 1+ years of programming experience. Lab equipment experience and scripting in Python, Perl, TCL or Shell are preferred.
oscilloscope, multimeter, Python, Perl, TCL, Shell
Cross-Functional Engineer, Staff
Toronto, ON +1Qualcomm Canada ULC
4+ YOECandidates need a bachelor's, master's or PhD in Electrical Engineering with analog or mixed-signal chip design experience and several years of ASIC design or verification work. They also need strong high-speed SerDes knowledge, SystemVerilog and EDA tool skills.
Cadence, SPICE, MATLAB, Verilog, VHDL, SystemVerilog
Analog Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ YOECandidates need a Master's or PhD in electrical engineering (or a Bachelor's with 2+ years of analog or mixed-signal design), plus 8+ years of ASIC design or related work and silicon-proven analog circuit experience in advanced CMOS. Strong skills in Cadence, SPICE, MATLAB or Verilog-A are expected.
Cadence ADE, MATLAB, SPICE, Verilog-A
Verification Engineer (Engineer–Senior Level)
Toronto, ONQualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in science or engineering with 2+ years of ASIC design or verification experience, or a master's with 1+ year, or a PhD. Strong SystemVerilog and UVM skills, constrained random verification experience and clear communication are required.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
Physical Design Engineer, Staff
Toronto, ONQualcomm Canada ULC
7+ YOECandidates need 7+ years of physical design experience and a Bachelor's in Electrical or Computer Engineering or equivalent. Low-power, SoC and advanced technology node experience are desired, along with strong analytical, scripting and collaboration skills.
EDA tools
Sr ASIC Design Verification Engineer, Low Power AI
Markham, ONQualcomm Canada ULC
2+ YOEQualcomm Canada ULC needs candidates with a bachelor's, master's or PhD and 2 to 4+ years of ASIC work, depending on degree. Expert skill in Verilog, SystemVerilog, UVM and C, plus a deep understanding of ASIC/VLSI concepts, is required.
SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl
Staff Verification Engineer, Compute Subsystems
Markham, ONQualcomm Canada ULC
5+ YOECandidates need a bachelor's, master's, or PhD in engineering or science with several years of ASIC design or verification experience, plus strong UVM and SystemVerilog skills, bus protocol knowledge, and scripting in Perl or Python.
UVM, Perl, Python, C
FY27 Intern - Camera Design Implementation Intern - Canada (16 months)
Vancouver, BCQualcomm Canada ULC
Candidates need to be enrolled in a bachelor's degree in engineering, computer science or a related field, with an expected graduation of November 2028 or later. Strong scripting skills and knowledge of ASIC design flow are needed.
synthesis tools, static timing analysis tools, formal verification tools
Camera Design Engineer
Vancouver, BCQualcomm Canada ULC
3+ YOECandidates need a bachelor's, master's or PhD in a computer, electrical or related engineering field, with 4 to 2 years of hardware or related experience depending on degree. Verilog or VHDL RTL design, design verification and bus protocol experience are key.
Verilog, VHDL, TCL, Perl, Python
ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a Bachelor's degree in engineering, science or a related field and 2+ years of ASIC design or verification work, or a new-grad co-op, internship or PEY background. Preferred skills include SystemVerilog, UVM, Verilog or VHDL, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python
ASICS Design Verification Engineer (Vancouver, Markham OR Remote)
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in engineering or science and 2+ years of ASIC design or verification experience. Preferred skills include SystemVerilog and UVM testbench development, RTL design, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python