“UVM” jobs in Canada – Page 5

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• 1mo

  Utility Forestry Technician

  Saskatoon, SK

  $250–$300/dayFull Time

  WC

  Wright Canada Holdings Ltd

  1+ YOECandidates need a forestry diploma or degree, or one or more years of utility vegetation management field experience, plus a valid Class 5 licence and a clean driving record. They must pass a drug test and communicate clearly with landowners and contractors.

  Service truck

  1mo

  Utility Forestry Technician

  Prince Albert, SK

  $250–$300/dayFull Time

  WC

  Wright Canada Holdings Ltd

  1+ YOECandidates need a forestry diploma or degree, or one or more years of utility vegetation management field experience, plus a valid Class 5 licence and a clean driving record. They must pass a drug test and communicate clearly with landowners and contractors.

  Service truck

  1mo

  Utility Forestry Technician

  North Battleford, SK

  $250–$300/dayFull Time

  WC

  Wright Canada Holdings Ltd

  1+ YOECandidates need a forestry diploma or degree, or one or more years of utility vegetation management field experience, plus a valid Class 5 licence and a clean driving record. They must pass a drug test and communicate clearly with landowners and contractors.

  Service truck

• 1mo

  Senior FPGA Design/Verification Engineer

  Ottawa, ON

  Full Time

  LO

  Lumentum Ottawa ULC

  Candidates need strong experience designing and simulating FPGA or ASIC logic in Verilog or SystemVerilog, plus synthesis, timing and clock domain crossing skills. Strong debugging, communication and attention to detail are also required.

  Verilog, SystemVerilog, Altera FPGA tools

• 1mo

  Mixed Signal Design Engineer

  Ottawa, ON

  $93k–$149k/yrFull Time

  CC

  Ciena Canada ULC

  Ciena Canada ULC needs a degree in electrical or computer engineering, computer science or a related science. Candidates need CMOS or BiCMOS design experience and skill with Cadence, Synopsys and Siemens EDA tools, plus SystemVerilog, Verilog-AMS, Python and C/C++.

  Cadence Virtuoso, Cadence Xcelium, Cadence AMS, Synopsys VCS, Synopsys StarRC, Siemens Questa

  1mo

  Senior ASIC Verification Engineer, onsite Kanata

  Ottawa, ON

  $109k–$174k/yrFull Time

  CC

  Ciena Canada ULC

  Ciena Canada ULC needs candidates with an engineering or science degree at the BEng/BSc or MEng/MSc level and familiarity with formal verification. Candidates should know standards such as OTN, B100G and Ethernet, and programming in Python, C, C++ or SystemC.

  Python, C, C++, Make, bash

• 1mo

  Sr Staff Engineer, SoC RTL Design

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  Candidates need deep knowledge of computer architecture and chip microarchitecture, plus hands-on RTL design in Verilog or VHDL and familiarity with full ASIC flows. Experience optimizing for power, performance and area, and working collaboratively on specifications and design reviews, is needed. Prior work on on-chip fabric or interconnect design is an asset.

  Verilog, VHDL, FPGA, UVM, emulation platforms

  1mo

  Design Verification Lead, AI Hardware

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  Candidates need experience leading ASIC or SoC verification through complex chip releases, plus knowledge of AI and machine learning hardware. They should be hands-on with UVM, SystemVerilog and cocotb, and able to plan tests that work from simulation to FPGA to silicon.

  UVM, SystemVerilog, cocotb, FPGA

• 1mo

  Senior Design Verification Engineer

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  2+ YOECandidates need a bachelor's degree in electrical engineering or a related field and 2 to 5 years of verifying complex chips. Hands-on SystemVerilog, UVM and C/C++ experience, including C/C++ integration with SystemVerilog, is required, as is authorization to work in Canada.

  SystemVerilog, UVM, C/C++, Python, Perl, FPGA emulation platform

• 1mo

  Staff/Sr. Staff Design Verification Engineer

  Toronto, ON

  

  Lightmatter

  8+ YOECandidates need a bachelor's degree in an engineering field and at least 8 years of design verification and SystemVerilog experience. Python experience of 2 or more years, expertise with the UVM library and experience with Xcelium, ModelSim, Questa or VCS are also required.

  Xcelium, ModelSim, Questa, VCS, UVM, SystemVerilog

• 1mo

  Senior ASIC Design Verification Engineer

  Remote in Canada

  Remote

  

  Ethernovia, Inc.

  10+ YOECandidates need a BS or MS in electrical engineering, computer science or a related field, and at least 10 years of ASIC verification experience. Required skills include SystemVerilog, UVM, Python, TCL and C/C++, plus strong debugging and communication abilities.

  Verilog, UVM, Python, TCL, C/C++, SystemC

7 companies