SoC Physical Design Implementation Lead
Markham, ONAMD, Inc.
Candidates need deep hands-on experience with place and route, static timing analysis, clock distribution and physical verification on large SoCs. Advanced process nodes, 3D stacking, and Synopsys, Cadence or Siemens CAD tools are preferred, along with Tcl, Perl or Shell scripting.
Synopsys tools, Cadence tools, Tcl, Perl, Shell
SoC DFX Scan / ATPG Engineer
Ottawa, ONAMD, Inc.
Candidates need a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, plus strong DFT fundamentals and ASIC design flow knowledge. Scripting in Python, Perl, Tcl, or Shell and Verilog/SystemVerilog familiarity are preferred.
Verilog, SystemVerilog, Python, Perl, Tcl
Firmware Engineer
Vancouver, BCAMD, Inc.
Candidates need strong C++, C and scripting skills, pre-silicon and post-silicon firmware experience, and an understanding of computer architecture. A Bachelor's, Master's or PhD in Electrical or Computer Engineering with relevant experience is required.
VCS, oscilloscope, logic analyzer, FPGA
Design Verification Engineer
Markham, ONAMD, Inc.
AMD asks for advanced ASIC functional verification experience and hands-on work on multiple projects or tapeouts. Candidates need Verilog, SystemVerilog, UVM, scripting skills, and a Bachelor's or Master's in Computer or Electrical Engineering.
Verilog, UVM, Makefiles, Perl, Python, Ruby
Silicon Design Engineer
Markham, ONAMD, Inc.
Candidates need a bachelor's degree in electrical or computer engineering, with a master's or PhD preferred. AMD wants hands-on ASIC firmware and hardware verification experience with UVM, SystemVerilog, C/C++ and bus protocols such as AXI and AHB.
UVM, Verilog, C-DPI, Python, Perl, Make
SoC Design Lead, Microarchitecture and Design Methodology
Markham, ONAMD, Inc.
Candidates need a strong foundation in computer architecture and digital design, along with static timing analysis, clock and power optimization knowledge. Experience with Verilog or SystemVerilog, and UVM preferred, plus strong communication and teamwork skills.
Verilog, SystemVerilog, UVM
Silicon Design Verification Engineer
Markham, ONAMD, Inc.
Candidates need a Bachelor's or Master's in Computer or Electrical Engineering, knowledge of digital design and computer architecture, and hands-on SystemVerilog, UVM and C++ or Python experience. Prior verification work and PCIe or AXI protocol knowledge are assets.
UVM, C++, Python, Formal verification tools
Senior ASIC RTL Design Engineer, AI Networking IP
Ottawa, ONAMD, Inc.
Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.
Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python
Principal ASIC Design Engineer
Markham, ONAMD, Inc.
Candidates need a track record of leading ASIC or silicon designs through multiple product tape-outs, plus deep RTL and microarchitecture experience. Strong communication skills and the ability to lead technical reviews are also required.
Verilog, SystemVerilog, Python, Perl, Tcl
Senior Firmware Engineer
Markham, ONAMD, Inc.
Candidates need extensive experience with microcontrollers and embedded C or assembly, strong low-level hardware and firmware interface knowledge, and a bachelor's or master's degree in electronics, computer engineering or another applied science.
Git, GitHub Actions, Python, RTOS, emulation platforms, RTL simulation tools
Design Verification Lead
Markham, ONAMD, Inc.
Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.
SystemVerilog, Verilog, UVM, Python, Perl