“TCL” jobs in Canada – Page 6

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• 1mo

  Senior ASIC RTL Design Engineer, AI Networking IP

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in computer or electrical engineering, and strong Verilog or SystemVerilog RTL design skills. Experience delivering ASIC or FPGA products, plus networking or high-speed interface knowledge, is preferred.

  Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python

  1mo

  3D IC and ADVANCED PACKAGING CAD ENGINEER

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering, experience with 3D-IC design and advanced packaging, and hands-on work with Synopsys 3DIC Compiler. Strong scripting skills and experience applying AI to CAD or hardware design are also needed.

  Synopsys 3DIC Compiler, Synopsys EDA tools, Cadence EDA tools, Linux/Unix, Python, TCL

  1mo

  SoC DFX Scan / ATPG Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a degree in electrical or computer engineering, a strong grasp of DFT fundamentals and ASIC design flows, and debugging skills. Experience with scan insertion, ATPG, Verilog/SystemVerilog and scripting in Python, Perl, Tcl or Shell is preferred.

  Verilog, SystemVerilog

  1mo

  DFT Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering, strong problem-solving skills, and good written and oral communication. Scripting in Perl, Python, Shell or C++, object-oriented programming, and digital circuit and VLSI knowledge are preferred.

  Perl, Python, TCL, C++, Shell

  1mo

  SoC DFX Scan / ATPG Engineer

  Ottawa, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a degree in electrical or computer engineering, a strong grasp of DFT fundamentals and ASIC design flows, and debugging skills. Experience with scan insertion, ATPG, Verilog/SystemVerilog and scripting in Python, Perl, Tcl or Shell is preferred.

  Verilog, SystemVerilog

  1mo

  Validation Lead-Fuse/SoC

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in electrical or computer engineering, plus silicon bring-up, eFuse or non-volatile memory experience. Strong scripting in Python, Perl or Tcl and cross-functional communication are also required.

  Python, Perl, Tcl, C, C++, SQL

  1mo

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs candidates with proven SoC implementation and tapeout experience, deep knowledge of equivalence checking and low power verification, and hands-on use of industry EDA tools. Strong scripting, debugging, leadership and communication skills are also required, along with a BS or MS in Electrical Engineering, ECE, EEE or a related field.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

  1mo

  Lead Physical Design Engineer, Place & Route

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need deep hands-on place-and-route experience on complex chip designs, including timing closure and physical verification. Experience with Synopsys Fusion Compiler, Cadence and Siemens EDA tools, plus TCL, Perl or Shell scripting, is preferred, and a Bachelor's or Master's degree in electrical or computer engineering is preferred.

  Synopsys Fusion Compiler, Cadence, Siemens EDA, TCL, Perl, Shell

  1mo

  SoC Physical Design Implementation Lead

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs seasoned physical design experience on advanced nodes, with hands-on place and route, timing and sign-off skills. Candidates should know Synopsys, Cadence and Siemens tools and scripting in Tcl, Perl or Shell; a Bachelor's or Master's in electrical or computer engineering is preferred.

  Synopsys tools, Cadence tools

  1mo

  Principal ASIC Design Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need a track record of leading ASIC or silicon designs through multiple tape-outs, plus deep RTL and microarchitecture skills. A bachelor's degree in an engineering or computer field is preferred, and a master's or PhD is desired.

  Verilog, SystemVerilog, Python, Perl, Tcl

• 1mo

  Training Coordinator

  Montréal, QC

  HybridFull Time

  

  Pomerleau: It specializes in building, infrastructure, and civil engineering sectors, undertaking major projects through alternative delivery methods.

  2+ YOECandidates need 2 to 5 years of administration, training or HR administration experience, plus Microsoft Office skills and quick learning of new software. Strong organization, attention to detail, communication skills and experience with learning management systems are needed; Cornerstone is an asset.

  Microsoft Office Suite, Cornerstone, Learning management system

• 1mo

  Sr. Memory Layout Engineer (7676)

  Ottawa, ON

  T

  TSMC

  8+ YOECandidates need a bachelor's or master's degree in a related field and 8+ years of advanced semiconductor memory layout experience. They need expertise with FinFET nodes, verification tools, custom layout CAD tools and scripting, and fluent written and spoken English.

  Cadence Virtuoso, Custom Compiler, Calibre, ICV, TCL, Cadence Skill

• 1mo

  Student Intern, IT Application Associate

  Toronto, ON

  $23–$30/hr

  

  Celestica International LP

  Candidates need to be enrolled in the third year of a four-year Electrical Engineering, Computer Engineering or Computer Science program. They need basic software development experience, strong analytical skills and good written and oral communication skills.

  C#, .NET, SQL Server, Oracle DB, Azure, PowerShell

• 1mo

  Accountant

  Midland, ON

  

  zffriedricP2: The company develops and produces intelligent seat belt and steering wheel systems, airbag modules and gas generators for all forms of mobility with…

  5+ YOECandidates need a bachelor's degree in accounting or finance and about five years of similar professional experience. They must be proficient in Excel and Microsoft Office and have SAP experience.

  SAP

  1mo

  Production Supervisor

  Midland, ON

  

  zffriedricP2: The company develops and produces intelligent seat belt and steering wheel systems, airbag modules and gas generators for all forms of mobility with…

  5+ YOE5+ MgmtCandidates need five years of management experience in a manufacturing setting, strong leadership and problem-solving skills, and excellent written and spoken English. Previous union workforce experience and Excel skills are also requested.

  Excel

  1mo

  Head of Operations Plant 1

  Midland, ON

  

  zffriedricP2: The company develops and produces intelligent seat belt and steering wheel systems, airbag modules and gas generators for all forms of mobility with…

  5+ YOE5+ MgmtCandidates need five or more years of management experience in a technical environment with proven leadership. A post-secondary diploma or degree in a technical field is preferred, and knowledge of electroplating and metal finishing is an asset.

  Leadership, Health and safety, Regulatory compliance, Health and safety regulations, Forecasting, Monitor operations in the leather industry

• 1mo

  FPGA Designer Coop (Waterdown, CAN)

  Waterdown, ON

  $25/hr

  

  L3Harris Technologies

  Candidates need to be enrolled in an accredited university co-op program in good standing, and able to obtain CGP clearance. They need basic VHDL, an understanding of timing closure, revision control experience, and strong English writing skills.

  Xilinx design tools, Questa Sim, VHDL, Git, SVN

• 1mo

  Senior DevOps Developer (PDSW scrum) [585]

  Burnaby, BC

  On-siteFull Time

  

  D-Wave Quantum

  5+ YOECandidates need 5+ years building and troubleshooting cloud and on-premises web environments on VMware, KVM or XCP-ng, plus Linux administration, Kubernetes and monitoring experience. They also need strong Python or similar scripting skills, source control and CI/CD experience, and a computer science or engineering background.

  Kubernetes, Linux, VMware, KVM, XCP-ng, Grafana

• 1mo

  Senior I/O Chiplet RTL Design Engineer

  Ottawa, ON

  Full Time

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  10+ YOECandidates need 10+ years of hands-on ASIC RTL design with tape-out ownership, strong SystemVerilog and Verilog skills, and experience with high-speed interfaces such as PCIe, Ethernet or die-to-die links. They also need synthesis, timing constraint and CDC/RDC expertise, plus scripting in Python or Tcl.

  SystemVerilog, Verilog, Python, Tcl

  1mo

  Senior FPGA Design Engineer

  Ottawa, ON

  Full Time

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  10+ YOECandidates need about 10 to 15 years of hands-on FPGA design experience and strong current SystemVerilog skills. They must handle clock domain crossings, configure synthesis tools, write SDC constraints, and analyze synthesis reports, and be available to work on-site in Ottawa.

  SystemVerilog, SDC

• 1mo

  Senior Hardware Engineer

  Burnaby, BC

  Full Time

  

  LMI Technologies

  5+ YOECandidates need a bachelor's degree in electrical engineering and at least five years designing and testing digital logic such as FPGAs or ASICs. Hands-on experience with VHDL or Verilog, high-speed interfaces and self-verifying simulation environments is required.

  Vivado, Chipscope, Logic analyzers, Oscilloscopes, Xilinx IP, Intel FPGA

• 1mo

  FPGA Engineer

  Ottawa, ON

  $105k–$145k/yrFull Time

  

  Q-Block Computing: Imagine instruments precise enough to probe this reality—to ask whether the cosmos operates according to Nature’s own algorithms.

  4+ YOECandidates need a related engineering degree, 4+ years of professional FPGA design and verification experience, and hands-on work with Vivado, Quartus or Lattice toolchains. They also need strong high-speed digital design skills and proficiency with oscilloscopes, logic analyzers and signal generators.

  Xilinx Vivado, Intel Quartus, Lattice toolchain, oscilloscope, logic analyzer, signal generator

• 1mo

  FPGA Designer

  Sainte-Anne-de-Bellevue, QC

  Full Time

  

  MDA

  5+ YOECandidates need a bachelor's degree in electrical engineering or equivalent and five years of FPGA or ASIC design experience. They need VHDL skills, tool knowledge (Synplify, Questa, Vivado, Libero), Linux scripting, and bilingual English and French communication.

  Synplify, Modelsim, Questa, Vivado, Libero, Jira

• 1mo

  Software Release QA Specialist

  Burnaby, BC

  $80k–$115k/yrFull Time

  ?

  *Early Careers Candidates with 0–2 years of professional experience, including recent graduates, are encouraged to apply.*; Job Experience Required:; 3 - 5 years of software testing or developing experience

  DNS, DHCP, VMware, Linux, Ethereal, VPN

12 companies