“System Verilog” jobs in Canada – Page 8

No matching filters. Try another name.

Results

• 1mo

  Principal Engineer - Analog Design

  Toronto, ON +1

  $107k–$157k/yrFull Time

  MC

  Microchip - Canada

  5+ YOECandidates need a Master's or PhD in electrical engineering and at least 5 years of analog and mixed-signal circuit experience. Microchip Technology prefers experience with ADCs, DACs, filters, PLLs, DLLs and high-speed I/Os, plus scripting in SKILL, Python, Perl or Tcl.

  Cadence, Verilog-A, SKILL, Python, Perl, Tcl

  1mo

  Ingénieur principal en analogique/ Principal Engineer - Analog Design

  Montréal, QC

  Full Time

  MC

  Microchip - Canada

  5+ YOECandidates need a master's or PhD in electrical engineering and at least 5 years of analog and mixed-signal design experience. Strong skills in high-speed circuits, Cadence IC tools, scripting and Verilog-A are expected.

  Cadence IC, Verilog-A, Skill, Python, Perl, Tcl

• 1mo

  Ingénieur principal du personnel technique – Conception analogique/ Senior Technical Staff Engineer - Analog Design

  Montréal, QC

  Full Time

  MS

  MCHP Semiconductor Canada ULC

  10+ YOEMaîtrise ou doctorat en génie électrique; Plus de 10 ans d’expérience en circuits intégrés analogiques et mixtes; Expérience en PLL/DLL, ADC/DAC et interfaces E/S haute vitesse

  Cadence IC, Verilog-A, Skill, Python, Perl, Tcl

  1mo

  Senior Engineer II - Physical Design

  Burnaby, BC

  $86k–$186k/yrFull Time

  MS

  MCHP Semiconductor Canada ULC

  7+ YOECandidates need a 4-year Electrical or Electronics Engineering degree and 7.5+ years of ASIC development experience. They need hands-on skill in synthesis, static timing and place and route for high-performance designs, plus Python, Perl or TCL scripting.

  Verilog, VHDL, Python, Perl, TCL

  1mo

  Senior Manager-Design Engineering

  Burnaby, BC +2

  Full Time

  MS

  MCHP Semiconductor Canada ULC

  12+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering, 12+ years of related experience and proven experience leading engineering teams. Strong coaching skills, debugging ability and Verilog or VHDL design experience are required; SOC, communication protocols, Synopsys or Cadence tools and 28nm process experience are assets.

  Verilog, VHDL, Synopsys, Cadence

• 1mo

  Senior ASIC Design Engineer - Client IP

  Ottawa, ON

  $112k–$179k/yrFull Time

  CC

  Ciena Canada ULC

  5+ YOECandidates need an engineering degree at the bachelor or master level and 5+ years of SystemVerilog design and digital synthesis, timing closure and clock-crossing experience. Strong independent problem solving, English communication, and knowledge of verification and timing/power/area trade-offs are required.

  Git, Jira, Python, Make, bash

  1mo

  Senior ASIC Verification Engineer, onsite Kanata

  Ottawa, ON

  $109k–$174k/yrFull Time

  CC

  Ciena Canada ULC

  Ciena Canada ULC needs candidates with an engineering or science degree at the BEng/BSc or MEng/MSc level and familiarity with formal verification. Candidates should know standards such as OTN, B100G and Ethernet, and programming in Python, C, C++ or SystemC.

  Python, C, C++, Make, bash

• 1mo

  Senior NPU Architect

  Remote in Canada

  Remote

  

  EnCharge AI

  5+ YOECandidates need a BS or MS in EE, CS or a related field with 5-8 years of relevant experience, or a PhD with 2-4 years. Knowledge of computer architecture, digital design, AI/ML workloads, C/C++, Python and Verilog or SystemVerilog is required.

  C++ simulation framework, Verilog, Python

• 1mo

  Optical DSP Design Engineer

  Ottawa, ON

  CC

  Celero Communications, Inc.

  2+ YOECandidates need a strong background in digital signal processing, digital communications and fiber-optic systems, plus a Master's or PhD in electrical engineering, physics or mathematics. Two or more years of industry experience and programming in C/C++, Python or MATLAB are preferred.

  MATLAB, Python, C++, Verilog, VHDL, GitHub

  1mo

  DSP - FEC Design Engineer

  Ottawa, ON

  CC

  Celero Communications, Inc.

  Candidates need a strong background in coding theory, digital communications and error correction, plus experience with forward error correction for communication systems. A master's or PhD in a related field and programming skills in C/C++, Python or MATLAB are preferred.

  MATLAB, Python, C++, GitHub, Verilog, VHDL

• 1mo

  Power Architect

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  15+ YOECandidates need 15+ years of experience with power estimation tools, deep knowledge of power-gating, voltage domains and leakage control, and a record of reducing design power through architectural changes. Proficiency in Verilog, Design Compiler, C/C++ and Python is required.

  PowerArtist, PtPX, RTL Architect, PrimePower, Verilog HDL, Design Compiler

• 1mo

  Senior Embedded Software Designer

  Toronto, ON

  HybridFull Time

  

  Kepler Communications

  6+ YOECandidates need 6+ years of embedded software experience on high-reliability systems, strong C/C++ skills, and embedded Linux or RTOS experience. A bachelor's degree or equivalent practical experience is required.

  Git, Yocto, FreeRTOS

• 1mo

  Senior FPGA Designer

  Montréal, QC

  HybridFull Time

  E

  Exegy

  5+ YOEDiplôme en génie électronique, électrique ou informatique; Cinq ans ou plus d'expérience en conception FPGA; Maîtrise avancée du VHDL et/ou du Verilog

  Vivado, Git, Jenkins, Python, Linux

• 1mo

  Senior Digital Design Engineer

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  2+ YOECandidates need a bachelor's degree in electrical or electronics engineering, 2 to 5 years of digital design experience on complex chips, and hands-on SystemVerilog or Verilog RTL skills. PCIe or Ethernet IP experience and Python or Perl scripting are also required, and candidates must be authorized to work in Canada.

  SystemVerilog, Verilog, Synopsys, Cadence, Python, Perl

• 1mo

  Concepteur – Électronique Analogique & Digitale / Designer – Analog & Digital Electronics (future opportunities)

  Montréal, QC

  On-site

  

  Syntronic

  5+ YOEBaccalauréat en génie électrique ou électronique; 5 ans d'expérience en conception et validation de circuits; Maîtrise d'OrCAD/Allegro, Altium ou Xpedition

  OrCAD, Allegro, Altium, Xpedition, Matlab, SPICE

• 1mo

  FPGA Engineer

  Toronto, ON

  HybridFull Time

  

  Cerebras Systems

  5+ YOECerebras Systems needs candidates with 5+ years of production FPGA experience (or a Master's/PhD plus 3 years), Verilog skill in a Git repository, and strong FPGA place-and-route, timing closure and debug skills. Knowledge of TCP, RoCE and Wireshark, plus network switch familiarity, is also required.

  Verilog, Git, Wireshark, Arista, Juniper

• 1mo

  Senior ASIC (Front End) Design Engineer

  Toronto, ON

  Hybrid

  

  Ethernovia, Inc.

  10+ YOECandidates need a BS or MS in electrical engineering, computer science or a related field and 10+ years of ASIC RTL design or architecture experience. They must have built complex SoCs, know Verilog/SystemVerilog and simulation tools, and work well both independently and in teams.

  Verilog, Perl, TCL, C/C++, Make

  1mo

  Senior ASIC Design Verification Engineer

  Remote in Canada

  Remote

  

  Ethernovia, Inc.

  10+ YOECandidates need a BS or MS in electrical engineering, computer science or a related field, and at least 10 years of ASIC verification experience. Required skills include SystemVerilog, UVM, Python, TCL and C/C++, plus strong debugging and communication abilities.

  Verilog, UVM, Python, TCL, C/C++, SystemC

12 companies