IP Design PEY Intern
Toronto, ONFull Time
AS
Altera Semiconductor Technology Canada ULC
Candidates need to be currently pursuing a BS in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or a related field. They need at least 3 months of Verilog, SystemVerilog or VHDL design or verification experience and 3 months of Python, TCL, Perl, C or C++ experience.
Quartus Prime, Verilog, SystemVerilog, VHDL
IP Firmware Design Engineer
Toronto, ONFull Time
AS
Altera Semiconductor Technology Canada ULC
2+ YOECandidates need a bachelor's degree in an engineering or computer science field, 2+ years of digital hardware design or verification (SystemVerilog, Verilog or VHDL), and 2+ years of scripting or software programming (Python, TCL, Perl, C or C++).
Quartus Prime, SystemVerilog, Verilog, VHDL, Python, TCL