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Qualcomm Canada ULC
Candidates need a bachelor's degree in engineering, computer science or a related field, plus hands-on custom layout experience in Cadence Virtuoso or Synopsys Custom Compiler, including DRC/LVS work. Coding skills, comfort on Linux, and strong communication and problem-solving are needed.
Cadence Virtuoso, Synopsys Custom Compiler, Spectre, HSPICE, PrimeSim, ADE
Qualcomm Canada ULC
4+ YOECandidates need a bachelor's, master's or PhD in Electrical Engineering with analog or mixed-signal chip design experience and several years of ASIC design or verification work. They also need strong high-speed SerDes knowledge, SystemVerilog and EDA tool skills.
Cadence, SPICE, MATLAB, Verilog, VHDL, SystemVerilog
Lightmatter
5+ YOELightmatter needs candidates with a bachelor's degree in electrical or computer engineering and at least 5 years of ASIC or high-speed chip design experience, including multiple successful tape-outs. Candidates must know SystemVerilog or Verilog and have proven experience debugging logic and mixed-signal simulations.
SystemVerilog, Verilog, Synopsys VCS, Cadence Xcelium, Questa
Talan
7+ YOEAu moins sept ans d'expérience pertinente en ERP et en services SAP gérés; Expérience de la gestion de comptes et de la gouvernance client; Maîtrise d'ITIL et de la gouvernance des SLA, connaissance de SAP S/4HANA
SAP S/4HANA, SAP Joule, RISE with SAP, GROW with SAP
Talan
7+ YOECandidates need at least seven years of ERP experience with SAP AMS or managed services, plus ITIL-aligned service management and S/4HANA knowledge. A bachelor's degree is required, with a degree in IT preferred, and strong English communication is needed.
SAP S/4HANA, SAP Cloud ALM, SAP Solution Manager, SAP Joule
SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…
10+ YOECandidates need a Master's or PhD in Electrical Engineering, 10+ years in analog/mixed-signal CMOS design, and PLL design experience. Cadence tools and lab characterization experience are also required.
Cadence, SystemVerilog, Verilog-A
SiTime Corporation: SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the…
6+ YOECandidates need a Master's or PhD in Electrical Engineering and 6+ years of analog or mixed-signal IC design, including PLL design, CMOS or BiCMOS experience, and hands-on lab characterization.
Cadence, SystemVerilog, Verilog-A, AMS
Cisco Systems Canada Co.
8+ YOECandidates need a BSEE or higher engineering degree with substantial experience designing, simulating and measuring high-speed ICs in at least three listed areas, such as serial links, data converters, PLLs and amplifiers.
Cadence Virtuoso, Spectre, SpectreX, APS, Matlab, EMX
Cisco Systems Canada Co.
15+ YOECandidates need at least 15 years of related experience (or a master's with 10, or a PhD with 7) and hands-on design, simulation and measurement of high-speed ICs. They must have led a team on high-performance circuits.
Cadence Virtuoso, Spectre, Calibre, EMX, Matlab
Cisco Systems Canada Co.
8+ YOECandidates need a bachelor's with 8 years of related experience, a master's with 6, or a PhD with 3, plus hands-on experience designing, simulating and measuring high-speed ICs in at least three areas such as serial links, output drivers, PLLs, clock distribution, op-amps or equalization. Experience with FinFET/GAA technologies, high-frequency layout and Cadence tools is preferred.
Cadence Virtuoso, Spectre, Calibre, EMX, Matlab
Cisco Systems Canada Co.
12+ YOECandidates need a BSEE with 12+ years, an MS with 8+ years, or a PhD with 5+ years of experience. They must have high-speed IC design experience in at least three listed areas, such as serial links, PLLs, or equalization.
Cadence Virtuoso, Spectre, SpectreX, Calibre, EMX, Matlab
Cisco Systems Canada Co.
12+ YOECandidates need a bachelor's with 12 years, a master's with 8, or a PhD with 5 years of related experience, plus hands-on high-speed IC design across at least three areas such as SerDes, PLLs, clock distribution or equalization.
Cadence Virtuoso, Spectre, Calibre, EMX, Matlab
Cisco
8+ YOECandidates need a bachelor's with 8 years, a master's with 6, or a PhD with 3 years of related experience, plus hands-on design, simulation and measurement of high-speed ICs in at least three areas such as SerDes, PLLs, output drivers, clock distribution, amplifiers and equalization.
Cadence Virtuoso, Spectre, Calibre, EMX, Matlab
Cisco
5+ YOECandidates need a degree plus 5 to 12 years of related experience, depending on the degree level, and experience designing, simulating and measuring high-speed ICs across at least three of: SerDes, output drivers, PLLs, clock distribution, op-amps/PGAs or equalization. Experience with FinFET, layout and design tools is preferred.
Cadence Virtuoso, Spectre/APS/SpectreX, Calibre, EMX, Matlab
Cisco
7+ YOECandidates need a Bachelor's with 15 years, a Master's with 10 years, or a PhD with 7 years of related experience. They must have high-speed IC design experience in at least three areas and have led a high-performance circuit team.
Cadence Virtuoso, Calibre, EMX, Matlab
Cisco
12+ YOECisco candidates need 12+ years of experience with a BSEE, 8+ with an MS, or 5+ with a PhD. Experience in high-speed IC design in at least three areas such as SerDes, PLLs, output drivers, equalization and amplifiers is required.
Cadence Virtuoso, Spectre, Calibre, EMX, Matlab
Cisco
12+ YOECandidates need a BSEE with 12+ years of experience, or an equivalent MS or PhD background, plus hands-on design, simulation and measurement of high-speed ICs in at least three areas such as serial links, PLLs, drivers and data converters. Experience with FinFET technology, high-speed layout and Cadence Virtuoso is a plus.
Cadence Virtuoso, Spectre, SpectreX, APS, Matlab, EMX
Docebo: Imprint: https://www.docebo.com/company/imprint/
4+ YOECandidates need 4 to 6 years of B2B SaaS marketing experience, including at least 1 to 2 years targeting enterprise buyers with 5,000+ employees. They must have a record of measurable pipeline, partner programs that produced results, and planning field events that led to meetings.
Salesforce, HubSpot, Outreach, UserGems, Influ2, ReachDesk
11 companies