Principal Analog Mixed Signal Designer - 19497
Mississauga, ONS
Synopsys
5+ YOECandidates need a PhD with 5+ years or a Master's with 8+ years of hands-on analog IC design experience. Strong CMOS skills, detailed SerDes sub-circuit design experience and SPICE simulation expertise are required.
SPICE simulators, Verilog-A, schematic entry tools, physical layout tools, MATLAB, Python
Analog Design, Manager - 18463
Kanata, ONS
Synopsys
8+ YOE2+ MgmtCandidates need an M.A.Sc. with 8+ years or a PhD with 6+ years of analog or mixed-signal IC design experience, plus 2+ years of people management. They must have deep Multi-Gbps SerDes expertise, transistor-level design skills, and experience with SPICE, Verilog-A and layout.
SPICE, Verilog-A, Industry-standard simulation tools