“OVM” jobs in Canada

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• 6d

  ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham

  Vancouver, BC +1

  On-site

  QC

  Qualcomm Canada ULC

  2+ YOECandidates need a Bachelor's degree in engineering, science or a related field and 2+ years of ASIC design or verification work, or a new-grad co-op, internship or PEY background. Preferred skills include SystemVerilog, UVM, Verilog or VHDL, C or C++, and Python or Perl scripting.

  SystemVerilog, UVM, Verilog, VHDL, Perl, Python

  6d

  ASICS Design Verification Engineer (Vancouver, Markham OR Remote)

  Vancouver, BC +1

  QC

  Qualcomm Canada ULC

  2+ YOECandidates need a bachelor's degree in engineering or science and 2+ years of ASIC design or verification experience. Preferred skills include SystemVerilog and UVM testbench development, RTL design, C or C++, and Python or Perl scripting.

  SystemVerilog, UVM, Verilog, VHDL, Perl, Python

• 22d

  Staff Application Engineer

  Mississauga, ON

  S

  Synopsys

  7+ YOECandidates need a bachelor's degree in electrical and electronics engineering with 7+ years of applications, verification or emulation experience, or a master's with 5+ years. They need hands-on emulation platform experience, HDL and UVM skills, and scripting in Python, Perl or TCL.

  Synopsys ZeBu, Mentor Veloce, Cadence Palladium, Verilog, SystemVerilog, VHDL

• 22d

  RQ08570 - Technology Architect - Senior

  Toronto, ON

  RP

  Rubicon Path

  10+ YOECandidates need 10+ years of technical architecture and solution delivery experience, 5+ years in Ontario public-sector healthcare, and strong knowledge of health standards such as HL7 FHIR. Strong leadership, communication and stakeholder skills are also required.

  Oracle T7, Oracle Backup and Recovery Appliance, Oracle OVM, Docker, AWS, RedHat

• 23d

  Verification Engineer

  Markham, ON

  Full Time

  AI

  AMD, Inc.

  Candidates need strong SystemVerilog and UVM skills, experience with ASIC or SoC verification, and familiarity with constrained-random, coverage-driven and formal verification. A Bachelor's or Master's in computer or electrical engineering is required.

  UVM, Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal

• 28d

  Verification Engineer

  Markham, ON

  Full Time

  AM

  Advanced Micro Devices, Inc

  Candidates need strong SystemVerilog and UVM skills, solid ASIC/SoC verification experience, and familiarity with constrained-random, coverage-driven and formal (SVA) methods. A bachelor's or master's in computer or electrical engineering is required.

  Synopsys VCS, Cadence IES, Cadence IEV, Jasper, VC-Formal, Magellan

• 29d

  Engineer, Digital Design Verification

  Ottawa, ON

  Full Time

  S

  Semtech_Canada_Corporation

  2+ YOECandidates need a B.Sc. in Electrical or Computer Engineering and at least 2 years of industry experience. Semtech Canada Corporation expects knowledge of UVM-style verification, SystemVerilog, scripting in Python, TCL, Perl or C, and Linux.

  SystemVerilog, UVM, Python, TCL, Perl, Linux

  29d

  Senior Design/Verification Engineer

  Burlington, ON +1

  Full Time

  S

  Semtech_Canada_Corporation

  5+ YOECandidates need a B.Sc. in Electrical or Computer Engineering and 5+ years of industry experience, with expert knowledge of constrained random verification (UVM, OVM, AVM or VMM) and SystemVerilog. Scripting skills in Python, TCL, Perl or C and working knowledge of Linux are also required.

  SystemVerilog, UVM, Python, TCL, Perl, Linux

6 companies