FY27 Intern - Digital Design Engineering Intern - Canada (16 months)
Toronto, ONQualcomm Canada ULC
Candidates need to be working toward a bachelor's degree in engineering, computer science or a related field, with strong digital design fundamentals. Verilog or VHDL knowledge and scripting in Perl, Python or TCL are required, with DFT concepts, Tessent, C/C++ or SystemVerilog as assets.
Verilog, VHDL, Perl, Python, TCL, Siemens Tessent
DFT Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ YOECandidates need 10+ years of SoC experience in RTL, DFT or front-end roles, and extensive use of Siemens, Synopsys and Cadence DFT tools. Strong Verilog, VHDL and SystemVerilog skills, knowledge of JTAG, iJTAG and BIST standards, and TCL or Python scripting are expected.
Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL
DFT Engineer (Senior to Staff level)
Toronto, ONQualcomm Canada ULC
10+ YOECandidates need a bachelor's degree in an engineering or computer science field and 10+ years of SoC design experience in RTL, DFT or front-end work. They need strong knowledge of DFT tools, Verilog, VHDL and SystemVerilog, and standards such as JTAG, iJTAG and BIST.
Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL