FY27 Intern - Digital Design Engineering Intern - Canada (16 months)
Toronto, ONQualcomm Canada ULC
Candidates need to be working toward a bachelor's degree in engineering, computer science or a related field, with strong digital design fundamentals. Verilog or VHDL knowledge and scripting in Perl, Python or TCL are required, with DFT concepts, Tessent, C/C++ or SystemVerilog as assets.
Verilog, VHDL, Perl, Python, TCL, Siemens Tessent
FY27 Intern - Display IP FPGA Emulation Intern - Canada (4 months)
Markham, ONQualcomm Canada ULC
1+ YOECandidates need to be in study toward a bachelor's degree in computer engineering, engineering science, computer science or a related field, with at least one year of academic programming experience. Knowledge of RTL, Verilog or SystemVerilog, digital design and Linux is required, plus teamwork and communication skills.
FPGA, Verilog, Linux, Perl, Python, TCL
GPU Design Verification Engineer
Markham, ONQualcomm Canada ULC
2+ YOECandidates need a relevant engineering or computer science degree plus years of hardware or software experience, depending on degree level. They need SystemVerilog, UVM, C/C++ and verification skills such as test planning, simulation and debug.
UVM, Veloce, Palladium, Zebu, FPGA, Python
Senior Director, Technology
Ottawa, ONQualcomm Canada ULC
10+ YOECandidates need a bachelor's in electrical engineering with 10 years of ASIC or IP development experience, or a master's with 8 years. They also need hands-on knowledge of Ethernet, UALink and OTN, HDL languages, SystemVerilog UVM and verification methods.
SystemVerilog, Verilog, VHDL, UVM, Unix/Linux, SVN
FY27 Intern - Display IP Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
1+ YOECandidates need to be enrolled in a bachelor's program in electrical, computer or engineering science, or a related field, with a graduation date of November 2028 or later. They need programming experience in C, C++ or Python, knowledge of RTL, Verilog or SystemVerilog and digital design, and good communication and teamwork skills.
Verilog, VHDL, Perl, Python, TCL, GNU Make
FY27 Intern - Edge AI and Display Hardware Architecture Development Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
Qualcomm Canada ULC needs candidates enrolled in an engineering or computer science bachelor's program, available May/June 2027 to August/September 2028 and graduating November 2028 or later. Strong analytical skills, programming in C/C++ or Python, and HW modeling and simulation experience are required.
Verilog, VHDL, C/C++, Python, HW simulation tools, HW CAD tools
Camera Design Engineer
Vancouver, BCQualcomm Canada ULC
3+ YOECandidates need a bachelor's, master's or PhD in a computer, electrical or related engineering field, with 4 to 2 years of hardware or related experience depending on degree. Verilog or VHDL RTL design, design verification and bus protocol experience are key.
Verilog, VHDL, TCL, Perl, Python
ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a Bachelor's degree in engineering, science or a related field and 2+ years of ASIC design or verification work, or a new-grad co-op, internship or PEY background. Preferred skills include SystemVerilog, UVM, Verilog or VHDL, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python
ASICS Design Verification Engineer (Vancouver, Markham OR Remote)
Vancouver, BC +1Qualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in engineering or science and 2+ years of ASIC design or verification experience. Preferred skills include SystemVerilog and UVM testbench development, RTL design, C or C++, and Python or Perl scripting.
SystemVerilog, UVM, Verilog, VHDL, Perl, Python