Lead Digital Verification Engineer
Montréal, QCCadence
Candidates need a Bachelor's degree in electrical, computer engineering or computer science, plus knowledge of verification methodologies, metric driven verification, UVM, SystemVerilog assertions and the digital design flow. A Master's degree, UVM coding experience, scripting skills and protocol knowledge such as PCIe, USB or Ethernet are preferred.
SystemVerilog, UVM, Python, Perl, Cadence tools
Lead Digital Verification Engineer
Mount Royal, SKCadence
Candidates need an engineering degree in electrical, computer or computer science, plus understanding of verification methodologies such as UVM and metric-driven verification. Strong problem-solving skills, English communication and experience with SystemVerilog assertions are required.
SystemVerilog, UVM, Python, Perl, Ruby, Cadence tools
Lead Digital Verification Engineer
Mount Royal, SKCadence
Candidates need an engineering degree in electrical, computer or computer science, plus understanding of verification methodologies such as UVM and metric-driven verification. Strong problem-solving skills, English communication and experience with SystemVerilog assertions are required.
SystemVerilog, UVM, Python, Perl, Ruby, Cadence tools