Physical Design Engineer
Vancouver, BCAdvanced Micro Devices, Inc
Candidates need a bachelor's or master's degree in computer or electrical engineering and hands-on ASIC physical design experience from RTL to GDSII. Strong Verilog, timing analysis, low-voltage design and advanced-node tape-out experience (3nm to 16nm) are preferred.
Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog
Static Timing Analysis / Full Chip Timing Engineer
Markham, ONAdvanced Micro Devices, Inc
Candidates need a BS, MS or PhD in Electrical Engineering, Computer Engineering or a related field, with full-chip timing experience preferred. Strong skill in multi-corner timing closure, clock architecture, ECO generation and scripting-based automation is expected.
DFT, Root cause analysis, Collaboration, Communication skills, Electrical engineering, Computer engineering
Physical Design Engineer
Markham, ONAdvanced Micro Devices, Inc
Candidates at Advanced Micro Devices need ASIC physical design experience from RTL to GDSII, strong Verilog and timing analysis skills, and hands-on tape-out experience on 3nm to 16nm SoCs. They also need experience with Synopsys, Cadence or Mentor Graphics CAD tools and a bachelor's or master's degree in electrical or computer engineering.
Synopsys tools, Cadence tools, Mentor Graphics tools, Verilog
STA/Constraints Engineer
Vancouver, BCAdvanced Micro Devices, Inc
Candidates need industry experience in static timing analysis, constraints and timing signoff, plus expert use of Synopsys PrimeTime and GCA. Scripting in Perl, TCL, Shell or Python, and a degree in microelectronics or a related field, are preferred.
GCA, ICC2, Verilog, Perl, TCL, Python