DSP Systems Engineer, Staff
Toronto, ONQualcomm Canada ULC
4+ YOECandidates need a Bachelor's in engineering or a related field with 4+ years of systems engineering experience, or a Master's with 3+ years, or a PhD with 2+ years. Strong MATLAB, Python and C/C++ skills, plus DSP architecture experience in mixed-signal SerDes, are required.
MATLAB, Python, C/C++, RTL simulation tools
Optical System Engineer, Senior Staff
Ottawa, ONQualcomm Canada ULC
4+ YOECandidates need proven optical system design and simulation experience, preferably in MATLAB, and extensive hands-on lab testing of optical systems. Knowledge of Silicon Photonics, EAM/EML devices for IM/DD modules and DSP techniques is also required.
MATLAB, BERT, AWG, VNA, Optical boards
System Engineer, Application Engineering Principal
Ottawa, ON +1Qualcomm Canada ULC
12+ YOECandidates need a master's or PhD in an engineering or science field and 6 to 12+ years of experience in high-speed communications, DSP or SerDes. Deep knowledge of PAM4 signaling, IEEE 802.3 standards and MATLAB or Python is required.
MATLAB, Python
Cross-Functional Engineer, Staff
Toronto, ON +1Qualcomm Canada ULC
4+ YOECandidates need a bachelor's, master's or PhD in Electrical Engineering with analog or mixed-signal chip design experience and several years of ASIC design or verification work. They also need strong high-speed SerDes knowledge, SystemVerilog and EDA tool skills.
Cadence, SPICE, MATLAB, Verilog, VHDL, SystemVerilog
Analog Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ YOECandidates need a Master's or PhD in electrical engineering (or a Bachelor's with 2+ years of analog or mixed-signal design), plus 8+ years of ASIC design or related work and silicon-proven analog circuit experience in advanced CMOS. Strong skills in Cadence, SPICE, MATLAB or Verilog-A are expected.
Cadence ADE, MATLAB, SPICE, Verilog-A
DFT Engineer, Senior
Toronto, ONQualcomm Canada ULC
2+ YOECandidates need a bachelor's degree in an engineering or computer science field with 2+ years of hardware engineering experience, or a master's with 1+ year. They need hands-on DFT, ATPG, and test-pattern experience plus scripting skills.
Python, Tcl, Perl
FY27 Intern - Firmware/Embedded Software Engineering Internship - Canada (12 or 16 months)
Toronto, ONQualcomm Canada ULC
1+ YOECandidates need to be enrolled in a bachelor's degree in electrical or computer engineering, engineering science or computer science, with at least one year of academic programming experience in C, C++ or Python. Strong debugging, problem-solving and teamwork skills are needed, and availability must match the 12- or 16-month internship dates.
Git, Linux, FPGA, Verilog, SystemVerilog, GitHub Actions
FY27 Intern - Machine Learning Compiler & Performance Engineering Intern - Canada (16 months)
Markham, ONQualcomm Canada ULC
Candidates need proficiency in Python or C++, strong analytical and debugging skills, and good written and verbal communication. They must be pursuing a bachelor's degree in an engineering or computer science field, available May/June 2027 to August/September 2028, and expected to graduate November 2028 or later.
Git, Linux, SSH, CI/CD systems, PyTorch, ONNX
AI/ML Design Verification Engineer (Staff)
Markham, ONQualcomm Canada ULC
4+ YOECandidates need a bachelor's degree plus 4+ years of ASIC work, or a master's with 3+ years, or a PhD with 2+ years. They need SystemVerilog Assertions, a formal verification tool, UVM or SystemVerilog testing, and scripting in Python, Perl, Tcl or shell.
VC Formal, JasperGold, Questa Formal, SystemVerilog, UVM, Python
FY27 Intern - Edge AI and Display Hardware Architecture Development Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
Qualcomm Canada ULC needs candidates enrolled in an engineering or computer science bachelor's program, available May/June 2027 to August/September 2028 and graduating November 2028 or later. Strong analytical skills, programming in C/C++ or Python, and HW modeling and simulation experience are required.
Verilog, VHDL, C/C++, Python, HW simulation tools, HW CAD tools
SOC Design Engineer
Markham, ON +2Qualcomm Canada ULC
4+ YOECandidates need a degree in science or engineering and 4+ years of ASIC design, verification or integration work, with strong digital front-end design skills in Verilog, SystemVerilog and VHDL. Experience with power domains, clock domain crossing, low-power design and chip design tools is needed.
Spyglass, Design Compiler, Cadence LEC, Perl, TCL