Lead Digital Verification Engineer
Montréal, QCFull Time
C
Cadence
Candidates need a Bachelor's degree in electrical, computer engineering or computer science, plus knowledge of verification methodologies, metric driven verification, UVM, SystemVerilog assertions and the digital design flow. A Master's degree, UVM coding experience, scripting skills and protocol knowledge such as PCIe, USB or Ethernet are preferred.
SystemVerilog, UVM, Python, Perl, Cadence tools