Near-Memory Compute System Validation Engineer
Markham, ONQualcomm Technologies, Inc.
3+ YOECandidates need a degree in engineering or computer science and several years of ASIC or silicon validation work. They need strong debugging skills, solid C/C++ and Python, and a good grasp of SoC architecture and memory systems.
JTAG, kernel debuggers, lab instrumentation, validation tools, FPGA, emulation platforms
PST Validation Engineer
Markham, ONQualcomm Technologies, Inc.
2+ YOECandidates need a bachelor's degree in science or engineering and 2+ years of ASIC design, verification or validation work, or a master's with 1+ year. They need knowledge of mobile chip architecture, regression and PVT testing, and C and Python programming.
Lauterbach Trace32, JTAG, Python, C
DDR Validation Lead, Staff (AI Accelerator Platform)
Markham, ONQualcomm Technologies, Inc.
5+ YOECandidates need at least 5 years in DDR or memory subsystem validation or silicon bring-up, plus knowledge of LPDDR architectures, memory controllers and PHYs, and strong post-silicon debug skills. Qualcomm also requires a bachelor's, master's or PhD and C/C++ proficiency.
emulation platforms, FPGA, C, C++
Pre-Silicon Validation Engineer
Markham, ONQualcomm Technologies, Inc.
Candidates need a Bachelor's or Master's degree in an engineering, computer science or related field, 0-2+ years in ASIC verification, FPGA prototyping or hardware emulation, and strong skills in SystemVerilog, C/C++, Linux, and Python. Experience with RTL debugging and SoC architectures is also required.
SystemVerilog, C/C++, Python, Linux, Cadence Palladium, Siemens Veloce
System Validation Lead (Premium Mobile Platforms)
Markham, ONQualcomm Technologies, Inc.
8+ YOECandidates need 8+ years of SoC validation, bring-up, or system software experience, deep knowledge of modern SoC architectures such as ARM CPUs, memory and interconnects, and proven pre- and post-silicon validation and debug skills. Leadership of geographically distributed teams is required.
Veloce, RUMI, FPGA
SoC Infrastructure/NoC, Power & Performance Validation Engineer
Markham, ONQualcomm Technologies, Inc.
5+ YOECandidates need several years of ASIC design, validation or verification experience, with a strong grasp of on-chip interconnects, performance and power. Strong programming in C, C++, Python and assembly, plus JTAG and kernel debugging, are expected.
JTAG debuggers, kernel debuggers, state dump scripts, Python, C, C++