ASIC Digital Design, Sr Staff Engineer-19314
Markham, ONS
Synopsys
8+ YOECandidates need a BS or MS in electronics or electrical engineering with 8+ years of digital verification experience in VMM or UVM. Strong Verilog and SystemVerilog testbench skills, debugging ability, and familiarity with Python or Perl are required.
Verilog, SystemVerilog, UVM, VMM, Jira, Confluence