“SystemVerilog UVM” jobs in Canada – Page 3

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• 1mo

  Lead Digital Verification Engineer

  Mount Royal, SK

  Full Time

  C

  Cadence

  Candidates need an engineering degree in electrical, computer or computer science, plus understanding of verification methodologies such as UVM and metric-driven verification. Strong problem-solving skills, English communication and experience with SystemVerilog assertions are required.

  SystemVerilog, UVM, Python, Perl, Ruby, Cadence tools

  1mo

  Firmware Design Engineer

  Mount Royal, SK

  $74k/yrFull Time

  C

  Cadence

  Solide programmation en C/C++ et Python; Compréhension des principes de communication filaire; Connaissance des circuits mixtes et du traitement numérique du signal

  Firmware, Work independently, Leadership, C, C++, Python

  1mo

  Ingénieur en conception de micrologiciel - Firmware Design Engineer

  Mount Royal, SK

  $74k/yrFull Time

  C

  Cadence

  Programmation solide en C/C++ et Python; Connaissance des communications filaires; Connaissance de la conception de circuits mixtes et du traitement numérique du signal

  Firmware, Work independently, Leadership, C, C++, Python

  1mo

  Ingénieur en conception de micrologiciel - Firmware Design Engineer

  Mount Royal, SK

  $74k/yrFull Time

  C

  Cadence

  Programmation solide en C/C++ et Python; Connaissance des communications filaires; Connaissance de la conception de circuits mixtes et du traitement numérique du signal

  Firmware, Work independently, Leadership, C, C++, Python

  1mo

  Lead Digital Verification Engineer

  Mount Royal, SK

  Full Time

  C

  Cadence

  Candidates need an engineering degree in electrical, computer or computer science, plus understanding of verification methodologies such as UVM and metric-driven verification. Strong problem-solving skills, English communication and experience with SystemVerilog assertions are required.

  SystemVerilog, UVM, Python, Perl, Ruby, Cadence tools

• 1mo

  Engineer, Digital Design Verification

  Ottawa, ON

  Full Time

  S

  Semtech_Canada_Corporation

  2+ YOECandidates need a B.Sc. in Electrical or Computer Engineering and at least 2 years of industry experience. Semtech Canada Corporation expects knowledge of UVM-style verification, SystemVerilog, scripting in Python, TCL, Perl or C, and Linux.

  SystemVerilog, UVM, Python, TCL, Perl, Linux

  1mo

  Senior Design/Verification Engineer

  Burlington, ON +1

  Full Time

  S

  Semtech_Canada_Corporation

  5+ YOECandidates need a B.Sc. in Electrical or Computer Engineering and 5+ years of industry experience, with expert knowledge of constrained random verification (UVM, OVM, AVM or VMM) and SystemVerilog. Scripting skills in Python, TCL, Perl or C and working knowledge of Linux are also required.

  SystemVerilog, UVM, Python, TCL, Perl, Linux

• 1mo

  Senior ASIC Design Verification Engineer - LPU

  Remote in Canada

  RemoteFull Time

  NC

  NVIDIA Canada Dev. Inc.

  8+ YOECandidates need a bachelor's degree in electrical engineering, computer science or computer engineering, or equivalent experience, plus 8 or more years in the industry. They need strong skills in SystemVerilog, UVM and chip design tools.

  VCS, Verdi, SystemVerilog, UVM, Perl, Python

• 1mo

  Senior FPGA Design/Verification Engineer

  Ottawa, ON

  Full Time

  LO

  Lumentum Ottawa ULC

  Candidates need strong experience designing and simulating FPGA or ASIC logic in Verilog or SystemVerilog, plus synthesis, timing and clock domain crossing skills. Strong debugging, communication and attention to detail are also required.

  Verilog, SystemVerilog, Altera FPGA tools

• 1mo

  Mixed Signal Design Engineer

  Ottawa, ON

  $93k–$149k/yrFull Time

  CC

  Ciena Canada ULC

  Ciena Canada ULC needs a degree in electrical or computer engineering, computer science or a related science. Candidates need CMOS or BiCMOS design experience and skill with Cadence, Synopsys and Siemens EDA tools, plus SystemVerilog, Verilog-AMS, Python and C/C++.

  Cadence Virtuoso, Cadence Xcelium, Cadence AMS, Synopsys VCS, Synopsys StarRC, Siemens Questa

• 1mo

  Design Verification Lead, AI Hardware

  Toronto, ON

  

  Tenstorrent: Tenstorrent is a next-generation computing company that builds computers for AI.

  Candidates need experience leading ASIC or SoC verification through complex chip releases, plus knowledge of AI and machine learning hardware. They should be hands-on with UVM, SystemVerilog and cocotb, and able to plan tests that work from simulation to FPGA to silicon.

  UVM, SystemVerilog, cocotb, FPGA

• 1mo

  Senior Design Verification Engineer

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  2+ YOECandidates need a bachelor's degree in electrical engineering or a related field and 2 to 5 years of verifying complex chips. Hands-on SystemVerilog, UVM and C/C++ experience, including C/C++ integration with SystemVerilog, is required, as is authorization to work in Canada.

  SystemVerilog, UVM, C/C++, Python, Perl, FPGA emulation platform

• 1mo

  Staff/Sr. Staff Design Verification Engineer

  Toronto, ON

  

  Lightmatter

  8+ YOECandidates need a bachelor's degree in an engineering field and at least 8 years of design verification and SystemVerilog experience. Python experience of 2 or more years, expertise with the UVM library and experience with Xcelium, ModelSim, Questa or VCS are also required.

  Xcelium, ModelSim, Questa, VCS, UVM, SystemVerilog

8 companies