Principal Engineer -Design
Saskatoon, SKMCHP Semiconductor Canada ULC
10+ YOECandidates need 10 years of experience in synthesis, static timing analysis and formal verification, plus tapeout experience on 16nm or smaller processes. Strong scripting skills and a degree in computer science or electrical/VLSI engineering are required.
Cadence Genus, TCL, Perl, Python, UPF, CPF
Sr Engineer I - Validation (Systems)
Burnaby, BCMCHP Semiconductor Canada ULC
5+ YOECandidates need at least 5 years of silicon or SoC validation experience, strong C/C++ and Python (or Tcl) skills, and hands-on lab work with high-speed test equipment. A bachelor's or master's degree in computer or electrical engineering or computer science is required.
Oscilloscopes, Protocol analyzers, Logic analyzers, FPGAs, Validation boards, Lab equipment
Principal Engineer - Validation (Systems)
Burnaby, BCMCHP Semiconductor Canada ULC
10+ YOECandidates need 10 years of silicon or SoC validation experience, strong C/C++ and Python skills, and hands-on lab experience with high-speed test equipment. A Bachelor's or Master's in electrical or computer engineering or computer science is required.
Oscilloscope, Protocol analyzer, Logic analyzer, FPGA, Emulation platform, Validation board
Engineer II- Product
Burnaby, BCMCHP Semiconductor Canada ULC
1+ YOEMCHP Semiconductor Canada ULC needs a BS or MS in Electrical Engineering or Engineering Physics, 1-2 years of related experience, hands-on lab skills with oscilloscopes, spectrum analyzers, BERTs and VNAs, and Python scripting for test automation.
oscilloscope, spectrum analyzer, BERT, VNA, Python, PCB
Senior SoC Design Engineer
Burnaby, BCMCHP Semiconductor Canada ULC
3+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.
Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl
Senior Technical Staff Engineer - Analog Design
Ottawa, ONMCHP Semiconductor Canada ULC
10+ YOECandidates need a Master's or Doctorate in Electrical Engineering or a related field and 10+ years of analog and mixed-signal IC design experience, including PLLs, DLLs, ADCs, DACs and high-speed I/O. Strong skills in Cadence tools, scripting and multi-site teamwork are required.
Cadence, Verilog-A, Skill, Python, Perl, Tcl
Ingénieur principal du personnel technique – Conception analogique/ Senior Technical Staff Engineer - Analog Design
Montréal, QCMCHP Semiconductor Canada ULC
10+ YOEMaîtrise ou doctorat en génie électrique; Plus de 10 ans d’expérience en circuits intégrés analogiques et mixtes; Expérience en PLL/DLL, ADC/DAC et interfaces E/S haute vitesse
Cadence IC, Verilog-A, Skill, Python, Perl, Tcl
Senior Manager-Design Engineering
Burnaby, BC +2MCHP Semiconductor Canada ULC
12+ YOECandidates need a Bachelor's or Master's in electrical or computer engineering, 12+ years of related experience and proven experience leading engineering teams. Strong coaching skills, debugging ability and Verilog or VHDL design experience are required; SOC, communication protocols, Synopsys or Cadence tools and 28nm process experience are assets.
Verilog, VHDL, Synopsys, Cadence