Analog Design, Principal Engineer- 18339
Markham, ONSynopsys
8+ YOECandidates need 8+ years of CMOS analog or mixed-signal design experience and strong expertise in transistor-level and SerDes circuits. Hands-on FinFET layout, SPICE and scripting skills, and knowledge of reliability and ESD design are also required.
SPICE simulators, EDA tools, Python, TCL
R&D Engineering , Sr Engineer
Vancouver, BCSynopsys
2+ YOECandidates need a bachelor's degree in a technical field and 2+ years of software development. They need strong C++, data structures and geometric algorithm skills, with meshing experience a strong plus.
C++
St Staff R&D Engineer
Waterloo, ONSynopsys
5+ YOECandidates need a bachelor's or master's degree in computer science or a related field, plus 5+ years of production software experience. Strong skills in C#, .NET, Python and Angular, and the ability to design software frameworks, are required.
Angular, Python, C#, React
R&D Engineering, Staff Engineer
Vancouver, BCSynopsys
5+ YOECandidates need a bachelor's degree in a technical field and 5+ years of software development (3+ with a master's or PhD). Strong C++ skills, performance optimization and GPU experience such as CUDA or OpenCL are needed.
C++, CUDA, OpenCL
Analog Design, Sr Architect - 18729
Markham, ONSynopsys
12+ YOECandidates need at least 12 years of related experience in high-speed interfaces and mixed-signal design. They also need skills in custom analog design, simulation, verification, debugging, and writing technical specifications.
Documentation, Communication skills, Troubleshooting, Debugging
Analog Design, Manager - 18463
Kanata, ONSynopsys
8+ YOE2+ MgmtCandidates need an M.A.Sc. with 8+ years or a PhD with 6+ years of analog or mixed-signal IC design experience, plus 2+ years of people management. They must have deep Multi-Gbps SerDes expertise, transistor-level design skills, and experience with SPICE, Verilog-A and layout.
SPICE, Verilog-A, Industry-standard simulation tools
Principal SI/PI Engineer - 18619
Mississauga, ONSynopsys
12+ YOECandidates need a bachelor's degree (master's or PhD preferred) in electrical engineering and 12+ years of high-speed SI/PI experience on SerDes links. They also need strong skills in simulation tools, lab measurement and scripting, plus proven technical leadership.
HSPICE, Keysight ADS, SystemVue, Ansys HFSS, SIwave, AEDT
Pre-Silicon Signoff Lead
Mississauga, ONSynopsys
10+ YOECandidates need an MSc or PhD in electrical or computer engineering and 10+ years of industry experience. They need deep knowledge of PCIe and Ethernet, SystemVerilog, UVM and scripting, plus proven leadership and mentoring skills.
SystemVerilog, UVM, Python, TCL, Perl, C++
Firmware Engineering Manager
Nepean, ONSynopsys
Synopsys needs candidates with a degree in computer science, electronics or a related field, and proven experience as a tech lead or engineering manager of embedded firmware teams. They must write production C for resource-constrained systems, debug RTL waveforms, and mentor engineers while communicating well with customers and stakeholders.
Firmware, Leadership, Coaching, Team leadership, RTL, Lead a team
Silicon Validation Software Engineer (Sr Staff)
Mississauga, ONSynopsys
8+ YOECandidates need 8+ years of software development in silicon validation or hardware test (or a master's with 6+ years), strong Python skills, and experience deploying validation tools. Git or GitLab, hardware debugging across the stack and lab experience are also needed.
Python, Git, GitLab, JTAG, I2C, SPI
Product Management , Staff
Vancouver, BCSynopsys
5+ YOECandidates need a technical degree or equivalent experience and at least five years of product management in photonics, optics or simulation software. They should understand photonic design workflows and simulation methods such as FDTD, and have experience with tools like OptoCompiler or Lumerical.
OptoCompiler, Lumerical